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3004 Commits
Author SHA1 Message Date
Unknown W. Brackets 217a1837ed irjit: Allow typical prefixes in vdiv/vasin/etc. 
Some of these behave strangely, but there are some common usages that work
fine.
 2023-08-13 18:10:07 -07:00
Henrik RydgårdandGitHub 2cdcc413b7 Merge pull request #17898 from unknownbrackets/irjit-vfputemps 
irjit: Cleanup/purge FPU/VFPU temps
 2023-08-13 21:08:00 +02:00
Henrik RydgårdandGitHub 5dcd14b17a Merge pull request #17901 from unknownbrackets/riscv-disasm 
riscv: Add debug log of block disasm
 2023-08-13 21:07:37 +02:00
Unknown W. BracketsandGitHub f03cd0b2ad Merge pull request #17899 from unknownbrackets/riscv-minor 
Minor RISC-V cleanups, frame profiler fix
 2023-08-13 11:19:42 -07:00
Henrik RydgårdandGitHub d6cdb6e5d9 Merge pull request #17900 from unknownbrackets/irjit-vsgelt 
irjit: Implement vsge/vslt
 2023-08-13 19:59:14 +02:00
Unknown W. Brackets 23c79f8e7f irjit: Implement vsge/vslt. 
These are not ideal especially for SIMD, but they do work.
Improves performance in Silent Hill on RISC-V by like 20%.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 5d20f2aabd irjit: Simplify VecDo3. 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 2b36e0a625 irjit: ZeroFpCond -> FpCondFromReg. 
We already have a zero reg, so this is more useful and symmetrical.
 2023-08-13 10:40:47 -07:00
Unknown W. Brackets 2bb67db43c riscv: Switch to the logBlocks model for disasm. 2023-08-13 10:37:21 -07:00
Unknown W. Brackets 8c036a889d riscv: Add debug log of block disasm. 2023-08-13 10:32:04 -07:00
Unknown W. Brackets 7cc6c5fa62 riscv: Fix load error w/o pointerify. 2023-08-13 10:20:28 -07:00
Unknown W. Brackets be938a850b riscv: Remove FMul safety check. 
Let's just see if everything's right, this bloats multiplies a lot.
Doesn't seem to impact perf a lot, though.
 2023-08-13 10:20:20 -07:00
Unknown W. Brackets fa53b80574 irjit: Cleanup/purge FPU/VFPU temps. 
A lot of cases are followed by an FMov that just moved the temp to a
regular register, from VFPU instructions playing safe about overlaps.
 2023-08-13 10:14:10 -07:00
Unknown W. Brackets 81f67c717c riscv: Fix block link for prev blocks. 
Oops, was just reversed so never linking.
 2023-08-12 10:48:39 -07:00
Unknown W. Brackets fcc90095f7 riscv: Enable block linking. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets 247788806a irjit: Add direct helper for start PC. 
It's annoying always fetching length too.
 2023-08-12 09:37:02 -07:00
Unknown W. Brackets b3cdf06c5a riscv: Write fixup on block invalidation. 2023-08-12 09:37:02 -07:00
Unknown W. Brackets 3757ebca2d irjit: Invalidate/finalize target blocks. 
Doesn't actually do anything yet, but adds plumbing.
 2023-08-12 09:37:02 -07:00
Henrik RydgårdandGitHub 2342c4522c Merge pull request #17875 from unknownbrackets/riscv-jit 
RISC-V: Implement a few more ops
 2023-08-09 09:30:15 +02:00
Henrik RydgårdandGitHub bac4e8d42d Merge pull request #17874 from unknownbrackets/irjit-exits 
IR: Simplify exits to ExitToConst when viable
 2023-08-09 09:11:52 +02:00
Unknown W. Brackets 2c13b6d973 riscv: Implement vc2i. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 28c58c1d24 irjit: Allow more forms of vmidt. 
Mildly worth it.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 4b9011e475 riscv: Reduce call bloat using temps. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets ddf3d02a3c riscv: Implement vi2uc. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 268adf1aa1 riscv: Implement scaled float/int convert. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 0b4e7d60f9 riscv: Implement ReverseBits in jit. 2023-08-08 23:17:32 -07:00
Unknown W. Brackets ad4cbbab8e riscv: Don't cache mipState on backend. 
Bad sign if we're trying to use it, anyway.
 2023-08-08 23:17:32 -07:00
Unknown W. Brackets 31ff23746c irjit: Prefer ExitToConst over ExitToReg. 2023-08-08 23:14:01 -07:00
Unknown W. Brackets 3f97545f99 irjit: Reduce exits from constants. 
This reduces bloat a bit, and may help with common funcs that enter short
loops.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets 5f9a8fd1a1 irjit: Rename IRRegCache to IRImmRegCache. 
For clarity, since it's not a native regcache.
 2023-08-08 23:05:14 -07:00
Unknown W. Brackets 1a92027810 riscv: Make Vec4Shuffle overlap safe. 2023-08-08 23:00:45 -07:00
Unknown W. Brackets e73c203984 irjit: Fix Vec4Shuffle overlap issue. 2023-08-08 23:00:39 -07:00
Henrik RydgårdandGitHub e9431d0d1e Merge pull request #17859 from unknownbrackets/irjit-vec4 
irjit: Use Vec4 a bit more
 2023-08-06 23:05:33 +02:00
Unknown W. Brackets 3dc71cff75 irjit: Keep a couple more ops in Vec4. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 6a1dbd4cde irjit: Allow Vec4 to be used with masks. 2023-08-06 13:46:24 -07:00
Unknown W. Brackets 2b964fd3b0 irjit: Handle more common Vec4 prefix cases. 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 79ca880ac7 irjit: Implement vqmul, add Vec4Blend. 
Should be useful more places.
 2023-08-06 13:38:00 -07:00
Unknown W. Brackets 85ee7c85c1 irjit: Allow masked vneg.q. 2023-08-06 13:38:00 -07:00
Henrik RydgårdandGitHub d90dbcb28e Merge pull request #17857 from unknownbrackets/ir-vfpuctrl 
irjit: Fix mfvc eating prefixes
 2023-08-06 17:56:22 +02:00
Unknown W. Brackets a32889d3ca irjit: Consistently dirty vfpuctrl in IR. 2023-08-06 08:36:19 -07:00
Unknown W. Brackets a29a35b91a irjit: Fix mfvc eating prefixes. 
It doesn't and shouldn't, which is why it's marked as not.
 2023-08-06 08:28:25 -07:00
Henrik RydgårdandGitHub 70622e0d4e Merge pull request #17853 from Nemoumbra/buildfix 
Buildfix for VS2017
 2023-08-06 14:29:04 +02:00
Nemoumbra c2f9ae2e16 Buildfix for VS2017 2023-08-06 15:06:54 +03:00
Unknown W. Brackets 93e3d35f5d irjit: Move more to IRNativeBackend, split. 2023-08-06 00:16:43 -07:00
Unknown W. Brackets 691799a0ca irjit: Centralize native jit compile dispatch. 2023-08-03 23:14:58 -07:00
Unknown W. Brackets 0d0029fc9d riscv: Add bitmanip ops to disasm. 2023-07-30 17:45:36 -07:00
Unknown W. Brackets c24dca12bb Build: Fix link issue for rv64 disasm. 2023-07-30 16:06:55 -07:00
Unknown W. BracketsandGitHub b03398a46c Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Henrik RydgårdandGitHub fa2b831dbc Merge pull request #17814 from unknownbrackets/riscv-jit-debug 
riscv: Implement block debug interface
 2023-07-30 23:42:14 +02:00
Henrik RydgårdandGitHub fa558b5b71 Merge pull request #17813 from unknownbrackets/riscv-jit-fixes 
Fix some typos and mistakes in RISC-V jit
 2023-07-30 23:41:13 +02:00