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3004 Commits
Author SHA1 Message Date
Unknown W. Brackets 1ccc2d5d2f x86jit: Fix address offsets with memview mask. 2023-08-21 09:03:10 -07:00
Unknown W. Brackets 40b3ff9573 x86jit: Fix spill issue. 2023-08-21 08:23:58 -07:00
Henrik RydgårdandGitHub 1e269c1d3c Merge pull request #17943 from unknownbrackets/x86-ir 
Add an x86/x64 backend for IR
 2023-08-21 09:21:37 +02:00
Unknown W. Brackets 538832940a x86jit: Implement some shifts. 2023-08-21 00:07:42 -07:00
Henrik RydgårdandGitHub 61bf366d30 Merge pull request #17942 from unknownbrackets/irjit-clobber 
irjit: Fix regalloc clobber on exit
 2023-08-21 08:04:50 +02:00
Unknown W. Brackets 2b914046ff x86jit: Implement most exits. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 104b6d8c15 x86jit: Implement some basic arithmetic. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 5045cf012e x86jit: Fix flushing of zero register. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 08ea31f405 x86jit: Improve debug disasm. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 4e7f8cf213 x86jit: Implement load/store. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets a47b4424e5 x86jit: Fix some silly mistakes. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 4e3f3860f9 x86jit: Stub out op categories to files. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 622c69dbb9 x86jit: Expose option to select new IR based jit. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets c491f701ba x86jit: Add initial IR-based jit backend. 
It works, but pretty slow in some parts with everything stubbed.
 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 81e24a9fee irjit: Fix regalloc clobber on exit. 2023-08-20 22:12:52 -07:00
Unknown W. Brackets 8dfc2f04d7 riscv: Use a single reg for LO/HI. 
This is the same optimization we have for arm64, basically.
 2023-08-20 14:49:09 -07:00
Henrik RydgårdandGitHub 629d46ef5b Merge pull request #17938 from unknownbrackets/riscv-centralize 
Centralize IR regcache from RISC-V
 2023-08-20 23:47:02 +02:00
Henrik RydgårdandGitHub 6554b3eb75 Merge pull request #17939 from unknownbrackets/ir-vec-minor 
irjit: Implement vtfm 4x4 using dots
 2023-08-20 23:40:04 +02:00
Unknown W. Brackets 82fb41cba0 irjit: Implement vtfm 4x4 using dots. 2023-08-20 13:50:02 -07:00
Unknown W. Brackets 36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets e30fb82a64 riscv: Remove some unused reg funcs. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 32d8f6196f irjit: Cut time flushing imm regs. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets 552cd88938 irjit: Skip some work in PurgeTemps. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets 57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Henrik RydgårdandGitHub cd1c5beb60 Merge pull request #17934 from unknownbrackets/riscv-centralize 
RISC-V: Centralize IR regcaches
 2023-08-20 14:49:18 +02:00
Unknown W. Brackets 161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
Unknown W. Brackets f3d4bd8c11 riscv: Centralize reg-as-pointer. 2023-08-19 21:24:36 -07:00
Unknown W. Brackets bd1d93ae6f irjit: Cleanup Write() calls with extra const. 
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
 2023-08-19 16:23:42 -07:00
Unknown W. Brackets 92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
Unknown W. Brackets b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Henrik Rydgård 1b2cffe632 Address feedback 2023-08-14 11:06:20 +02:00
Henrik Rydgård ff6e118fff Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically. 2023-08-14 11:02:29 +02:00
Henrik RydgårdandGitHub 1beb01af6a Merge pull request #17905 from unknownbrackets/irjit-opt 
irjit: Implement some missing, handle partial Vec4s more
 2023-08-14 07:49:45 +02:00
Henrik RydgårdandGitHub 63b3b31feb Merge pull request #17906 from unknownbrackets/riscv-blocklink 
riscv: Fix crash on clear icache
 2023-08-14 07:42:38 +02:00
Henrik RydgårdandGitHub a7bc70834c Merge pull request #17907 from unknownbrackets/riscv-minor 
riscv: Implement vs2i
 2023-08-14 07:41:45 +02:00
Unknown W. Brackets 52cc38bf2a riscv: Implement vs2i. 2023-08-13 18:27:19 -07:00
Unknown W. Brackets 3f8f8d36d9 riscv: Fix crash on clear icache. 
Oops, can't avoid marking all blocks invalid.  Luckily a syscall should
always take more bytes than the bail invalidated block code.
 2023-08-13 18:25:46 -07:00
Unknown W. Brackets 159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 5729de90d2 irjit: Use more partial Vec4s / Vec4Blend. 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets e0be6858b8 irjit: Implement vcrs.t. 
As used in Jeanne d'Arc.
 2023-08-13 18:10:12 -07:00