preserve-emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2026-07-11 01:25:07 +02:00
Code Issues Packages Projects Releases Wiki Activity

x86jit: Stub out op categories to files.

Browse Source
This commit is contained in:
Unknown W. Brackets
2023-08-20 19:15:44 -07:00
parent 622c69dbb9
commit 4e3f3860f9
16 changed files with 1018 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
CMakeLists.txt
+6
View File
@@ -1612,6 +1612,12 @@ list(APPEND CoreExtra
Core/MIPS/x86/RegCacheFPU.cpp
Core/MIPS/x86/RegCacheFPU.h
Core/MIPS/x86/X64IRAsm.cpp
Core/MIPS/x86/X64IRCompALU.cpp
Core/MIPS/x86/X64IRCompBranch.cpp
Core/MIPS/x86/X64IRCompFPU.cpp
Core/MIPS/x86/X64IRCompLoadStore.cpp
Core/MIPS/x86/X64IRCompSystem.cpp
Core/MIPS/x86/X64IRCompVec.cpp
Core/MIPS/x86/X64IRJit.cpp
Core/MIPS/x86/X64IRJit.h
Core/MIPS/x86/X64IRRegCache.cpp
Core/Core.vcxproj
+6
View File
@@ -606,6 +606,12 @@
<ClCompile Include="MIPS\RiscV\RiscVJit.cpp" />
<ClCompile Include="MIPS\RiscV\RiscVRegCache.cpp" />
<ClCompile Include="MIPS\x86\X64IRAsm.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompALU.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompBranch.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompFPU.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompLoadStore.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompSystem.cpp" />
<ClCompile Include="MIPS\x86\X64IRCompVec.cpp" />
<ClCompile Include="MIPS\x86\X64IRJit.cpp" />
<ClCompile Include="Replay.cpp" />
<ClCompile Include="Compatibility.cpp" />
Core/Core.vcxproj.filters
+18
View File
@@ -1252,6 +1252,24 @@
<ClCompile Include="MIPS\x86\X64IRJit.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompBranch.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompFPU.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompLoadStore.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompSystem.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompVec.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\X64IRCompALU.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="ELF\ElfReader.h">
Core/MIPS/RiscV/RiscVCompBranch.cpp
-1
View File
@@ -15,7 +15,6 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Core/MemMap.h"
#include "Core/MIPS/RiscV/RiscVJit.h"
#include "Core/MIPS/RiscV/RiscVRegCache.h"
Core/MIPS/RiscV/RiscVCompFPU.cpp
-1
View File
@@ -15,7 +15,6 @@
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Core/MemMap.h"
#include "Core/MIPS/RiscV/RiscVJit.h"
#include "Core/MIPS/RiscV/RiscVRegCache.h"
Core/MIPS/x86/X64IRCompALU.cpp
+220
View File
@@ -0,0 +1,220 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "Common/CPUDetect.h"
#include "Core/MemMap.h"
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for integer / arithmetic / logic related instructions.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_Arith(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Add:
case IROp::Sub:
case IROp::AddConst:
case IROp::SubConst:
case IROp::Neg:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Assign(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Mov:
case IROp::Ext8to32:
case IROp::Ext16to32:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Bits(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::ReverseBits:
case IROp::BSwap16:
case IROp::BSwap32:
case IROp::Clz:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Compare(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Slt:
case IROp::SltConst:
case IROp::SltU:
case IROp::SltUConst:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_CondAssign(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::MovZ:
case IROp::MovNZ:
case IROp::Max:
case IROp::Min:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Div(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Div:
case IROp::DivU:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_HiLo(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::MtLo:
case IROp::MtHi:
case IROp::MfLo:
case IROp::MfHi:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Logic(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::And:
case IROp::Or:
case IROp::Xor:
case IROp::AndConst:
case IROp::OrConst:
case IROp::XorConst:
case IROp::Not:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Mult(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Mult:
case IROp::MultU:
case IROp::Madd:
case IROp::MaddU:
case IROp::Msub:
case IROp::MsubU:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Shift(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Shl:
case IROp::Shr:
case IROp::Sar:
case IROp::Ror:
case IROp::ShlImm:
case IROp::ShrImm:
case IROp::SarImm:
case IROp::RorImm:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRCompBranch.cpp
+82
View File
@@ -0,0 +1,82 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for exits.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_Exit(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::ExitToConst:
case IROp::ExitToReg:
case IROp::ExitToPC:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_ExitIf(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::ExitToConstIfEq:
case IROp::ExitToConstIfNeq:
case IROp::ExitToConstIfGtZ:
case IROp::ExitToConstIfGeZ:
case IROp::ExitToConstIfLtZ:
case IROp::ExitToConstIfLeZ:
CompIR_Generic(inst);
break;
case IROp::ExitToConstIfFpTrue:
case IROp::ExitToConstIfFpFalse:
// Note: not used.
DISABLE;
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRCompFPU.cpp
+199
View File
@@ -0,0 +1,199 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for floating point related instructions.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_FArith(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FAdd:
case IROp::FSub:
case IROp::FMul:
case IROp::FDiv:
case IROp::FSqrt:
case IROp::FNeg:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FAssign(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FMov:
case IROp::FAbs:
case IROp::FSign:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FCompare(IRInst inst) {
CONDITIONAL_DISABLE;
constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC;
switch (inst.op) {
case IROp::FCmp:
case IROp::FCmovVfpuCC:
case IROp::FCmpVfpuBit:
case IROp::FCmpVfpuAggregate:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FCondAssign(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FMin:
case IROp::FMax:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FCvt(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FCvtWS:
case IROp::FCvtSW:
case IROp::FCvtScaledWS:
case IROp::FCvtScaledSW:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FRound(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FRound:
case IROp::FTrunc:
case IROp::FCeil:
case IROp::FFloor:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FSat(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FSat0_1:
case IROp::FSatMinus1_1:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FSpecial(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::FSin:
case IROp::FCos:
case IROp::FRSqrt:
case IROp::FRecip:
case IROp::FAsin:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_RoundingMode(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::RestoreRoundingMode:
RestoreRoundingMode();
break;
case IROp::ApplyRoundingMode:
ApplyRoundingMode();
break;
case IROp::UpdateRoundingMode:
// TODO: We might want to do something here?
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRCompLoadStore.cpp
+179
View File
@@ -0,0 +1,179 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "Core/MemMap.h"
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for load/store instructions.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_CondStore(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Store32Conditional:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FLoad(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::LoadFloat:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_FStore(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::StoreFloat:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Load(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Load8:
case IROp::Load8Ext:
case IROp::Load16:
case IROp::Load16Ext:
case IROp::Load32:
case IROp::Load32Linked:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_LoadShift(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Load32Left:
case IROp::Load32Right:
// Should not happen if the pass to split is active.
DISABLE;
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Store(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Store8:
case IROp::Store16:
case IROp::Store32:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_StoreShift(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Store32Left:
case IROp::Store32Right:
// Should not happen if the pass to split is active.
DISABLE;
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecLoad(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::LoadVec4:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecStore(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::StoreVec4:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRCompSystem.cpp
+142
View File
@@ -0,0 +1,142 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include "Common/Profiler/Profiler.h"
#include "Core/Core.h"
#include "Core/HLE/HLE.h"
#include "Core/HLE/ReplaceTables.h"
#include "Core/MemMap.h"
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_Basic(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Downcount:
//ADD(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG), Imm32(-(s32)inst.constant));
SUB(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32((s32)inst.constant));
break;
case IROp::SetConst:
regs_.SetGPRImm(inst.dest, inst.constant);
break;
case IROp::SetConstF:
case IROp::SetPC:
case IROp::SetPCConst:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Breakpoint(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Breakpoint:
case IROp::MemoryCheck:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_System(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Syscall:
case IROp::CallReplacement:
case IROp::Break:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_Transfer(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::SetCtrlVFPU:
case IROp::SetCtrlVFPUReg:
case IROp::SetCtrlVFPUFReg:
case IROp::FpCondFromReg:
case IROp::FpCondToReg:
case IROp::FpCtrlFromReg:
case IROp::FpCtrlToReg:
case IROp::VfpuCtrlToReg:
case IROp::FMovFromGPR:
case IROp::FMovToGPR:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_ValidateAddress(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::ValidateAddress8:
case IROp::ValidateAddress16:
case IROp::ValidateAddress32:
case IROp::ValidateAddress128:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRCompVec.cpp
+130
View File
@@ -0,0 +1,130 @@
// Copyright (c) 2023- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "ppsspp_config.h"
#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
#include <algorithm>
#include "Core/MemMap.h"
#include "Core/MIPS/x86/X64IRJit.h"
#include "Core/MIPS/x86/X64IRRegCache.h"
// This file contains compilation for vector instructions.
//
// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
// Currently known non working ones should have DISABLE. No flags because that's in IR already.
// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
#define CONDITIONAL_DISABLE {}
#define DISABLE { CompIR_Generic(inst); return; }
#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
namespace MIPSComp {
using namespace Gen;
using namespace X64IRJitConstants;
void X64JitBackend::CompIR_VecArith(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Vec4Add:
case IROp::Vec4Sub:
case IROp::Vec4Mul:
case IROp::Vec4Div:
case IROp::Vec4Scale:
case IROp::Vec4Neg:
case IROp::Vec4Abs:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecAssign(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Vec4Init:
case IROp::Vec4Shuffle:
case IROp::Vec4Blend:
case IROp::Vec4Mov:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecClamp(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Vec4ClampToZero:
case IROp::Vec2ClampToZero:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecHoriz(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Vec4Dot:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
void X64JitBackend::CompIR_VecPack(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::Vec2Unpack16To31:
case IROp::Vec4Pack32To8:
case IROp::Vec2Pack31To16:
case IROp::Vec4Unpack8To32:
case IROp::Vec2Unpack16To32:
case IROp::Vec4DuplicateUpperBitsAndShift1:
case IROp::Vec4Pack31To8:
case IROp::Vec2Pack32To16:
CompIR_Generic(inst);
break;
default:
INVALIDOP;
break;
}
}
} // namespace MIPSComp
#endif
Core/MIPS/x86/X64IRJit.cpp
-42
View File
@@ -325,48 +325,6 @@ void X64JitBackend::LoadStaticRegisters() {
}
}
// TODO: Move out to files.
void X64JitBackend::CompIR_Arith(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Assign(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Basic(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Bits(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Breakpoint(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Compare(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_CondAssign(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_CondStore(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Div(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Exit(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_ExitIf(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FArith(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FAssign(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FCompare(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FCondAssign(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FCvt(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FLoad(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FRound(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FSat(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FSpecial(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_FStore(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_HiLo(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Load(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_LoadShift(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Logic(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Mult(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_RoundingMode(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Shift(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Store(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_StoreShift(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_System(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_Transfer(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecArith(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecAssign(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecClamp(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecHoriz(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecLoad(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecPack(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_VecStore(IRInst inst) { CompIR_Generic(inst); }
void X64JitBackend::CompIR_ValidateAddress(IRInst inst) { CompIR_Generic(inst); }
} // namespace MIPSComp
#endif
UWP/CoreUWP/CoreUWP.vcxproj
+6
View File
@@ -576,6 +576,12 @@
<ClCompile Include="..\..\Core\MIPS\x86\RegCache.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\RegCacheFPU.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRAsm.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompALU.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompBranch.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompFPU.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompLoadStore.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompSystem.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompVec.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRJit.cpp" />
<ClCompile Include="..\..\Core\MIPS\x86\X64IRRegCache.cpp" />
<ClCompile Include="..\..\Core\PSPLoaders.cpp" />
UWP/CoreUWP/CoreUWP.vcxproj.filters
+18
View File
@@ -192,6 +192,24 @@
<ClCompile Include="..\..\Core\MIPS\x86\X64IRAsm.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompALU.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompBranch.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompFPU.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompLoadStore.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompSystem.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRCompVec.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
<ClCompile Include="..\..\Core\MIPS\x86\X64IRJit.cpp">
<Filter>MIPS\x86</Filter>
</ClCompile>
android/jni/Android.mk
+6
View File
@@ -304,6 +304,12 @@ ARCH_FILES := \
$(SRC)/Core/MIPS/x86/RegCache.cpp \
$(SRC)/Core/MIPS/x86/RegCacheFPU.cpp \
$(SRC)/Core/MIPS/x86/X64IRAsm.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompALU.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompBranch.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompFPU.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompLoadStore.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompSystem.cpp \
$(SRC)/Core/MIPS/x86/X64IRCompVec.cpp \
$(SRC)/Core/MIPS/x86/X64IRJit.cpp \
$(SRC)/Core/MIPS/x86/X64IRRegCache.cpp \
$(SRC)/GPU/Common/VertexDecoderX86.cpp \
libretro/Makefile.common
+6
View File
@@ -803,6 +803,12 @@ ifeq ($(WITH_DYNAREC),1)
$(COREDIR)/MIPS/x86/RegCache.cpp \
$(COREDIR)/MIPS/x86/RegCacheFPU.cpp \
$(COREDIR)/MIPS/x86/X64IRAsm.cpp \
$(COREDIR)/MIPS/x86/X64IRCompALU.cpp \
$(COREDIR)/MIPS/x86/X64IRCompBranch.cpp \
$(COREDIR)/MIPS/x86/X64IRCompFPU.cpp \
$(COREDIR)/MIPS/x86/X64IRCompLoadStore.cpp \
$(COREDIR)/MIPS/x86/X64IRCompSystem.cpp \
$(COREDIR)/MIPS/x86/X64IRCompVec.cpp \
$(COREDIR)/MIPS/x86/X64IRJit.cpp \
$(COREDIR)/MIPS/x86/X64IRRegCache.cpp \
$(GPUDIR)/Common/VertexDecoderX86.cpp