diff --git a/CMakeLists.txt b/CMakeLists.txt index db9ae9f230..4d6033eada 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1612,6 +1612,12 @@ list(APPEND CoreExtra Core/MIPS/x86/RegCacheFPU.cpp Core/MIPS/x86/RegCacheFPU.h Core/MIPS/x86/X64IRAsm.cpp + Core/MIPS/x86/X64IRCompALU.cpp + Core/MIPS/x86/X64IRCompBranch.cpp + Core/MIPS/x86/X64IRCompFPU.cpp + Core/MIPS/x86/X64IRCompLoadStore.cpp + Core/MIPS/x86/X64IRCompSystem.cpp + Core/MIPS/x86/X64IRCompVec.cpp Core/MIPS/x86/X64IRJit.cpp Core/MIPS/x86/X64IRJit.h Core/MIPS/x86/X64IRRegCache.cpp diff --git a/Core/Core.vcxproj b/Core/Core.vcxproj index e011e967e8..bd3fb17ad7 100644 --- a/Core/Core.vcxproj +++ b/Core/Core.vcxproj @@ -606,6 +606,12 @@ + + + + + + diff --git a/Core/Core.vcxproj.filters b/Core/Core.vcxproj.filters index 27da24f9b4..15964c072c 100644 --- a/Core/Core.vcxproj.filters +++ b/Core/Core.vcxproj.filters @@ -1252,6 +1252,24 @@ MIPS\x86 + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + diff --git a/Core/MIPS/RiscV/RiscVCompBranch.cpp b/Core/MIPS/RiscV/RiscVCompBranch.cpp index f1126b0317..f8663a82c9 100644 --- a/Core/MIPS/RiscV/RiscVCompBranch.cpp +++ b/Core/MIPS/RiscV/RiscVCompBranch.cpp @@ -15,7 +15,6 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. -#include "Core/MemMap.h" #include "Core/MIPS/RiscV/RiscVJit.h" #include "Core/MIPS/RiscV/RiscVRegCache.h" diff --git a/Core/MIPS/RiscV/RiscVCompFPU.cpp b/Core/MIPS/RiscV/RiscVCompFPU.cpp index c0cec762c4..3e36371c29 100644 --- a/Core/MIPS/RiscV/RiscVCompFPU.cpp +++ b/Core/MIPS/RiscV/RiscVCompFPU.cpp @@ -15,7 +15,6 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. -#include "Core/MemMap.h" #include "Core/MIPS/RiscV/RiscVJit.h" #include "Core/MIPS/RiscV/RiscVRegCache.h" diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp new file mode 100644 index 0000000000..b80e05f46a --- /dev/null +++ b/Core/MIPS/x86/X64IRCompALU.cpp @@ -0,0 +1,220 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include "Common/CPUDetect.h" +#include "Core/MemMap.h" +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for integer / arithmetic / logic related instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_Arith(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Add: + case IROp::Sub: + case IROp::AddConst: + case IROp::SubConst: + case IROp::Neg: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Assign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Mov: + case IROp::Ext8to32: + case IROp::Ext16to32: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Bits(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ReverseBits: + case IROp::BSwap16: + case IROp::BSwap32: + case IROp::Clz: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Compare(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Slt: + case IROp::SltConst: + case IROp::SltU: + case IROp::SltUConst: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_CondAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::MovZ: + case IROp::MovNZ: + case IROp::Max: + case IROp::Min: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Div(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Div: + case IROp::DivU: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_HiLo(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::MtLo: + case IROp::MtHi: + case IROp::MfLo: + case IROp::MfHi: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Logic(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::And: + case IROp::Or: + case IROp::Xor: + case IROp::AndConst: + case IROp::OrConst: + case IROp::XorConst: + case IROp::Not: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Mult(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Mult: + case IROp::MultU: + case IROp::Madd: + case IROp::MaddU: + case IROp::Msub: + case IROp::MsubU: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Shift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Shl: + case IROp::Shr: + case IROp::Sar: + case IROp::Ror: + case IROp::ShlImm: + case IROp::ShrImm: + case IROp::SarImm: + case IROp::RorImm: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRCompBranch.cpp b/Core/MIPS/x86/X64IRCompBranch.cpp new file mode 100644 index 0000000000..d54c6f7acb --- /dev/null +++ b/Core/MIPS/x86/X64IRCompBranch.cpp @@ -0,0 +1,82 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for exits. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_Exit(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ExitToConst: + case IROp::ExitToReg: + case IROp::ExitToPC: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_ExitIf(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ExitToConstIfEq: + case IROp::ExitToConstIfNeq: + case IROp::ExitToConstIfGtZ: + case IROp::ExitToConstIfGeZ: + case IROp::ExitToConstIfLtZ: + case IROp::ExitToConstIfLeZ: + CompIR_Generic(inst); + break; + + case IROp::ExitToConstIfFpTrue: + case IROp::ExitToConstIfFpFalse: + // Note: not used. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRCompFPU.cpp b/Core/MIPS/x86/X64IRCompFPU.cpp new file mode 100644 index 0000000000..e143865ca1 --- /dev/null +++ b/Core/MIPS/x86/X64IRCompFPU.cpp @@ -0,0 +1,199 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for floating point related instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_FArith(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FAdd: + case IROp::FSub: + case IROp::FMul: + case IROp::FDiv: + case IROp::FSqrt: + case IROp::FNeg: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FMov: + case IROp::FAbs: + case IROp::FSign: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FCompare(IRInst inst) { + CONDITIONAL_DISABLE; + + constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC; + + switch (inst.op) { + case IROp::FCmp: + case IROp::FCmovVfpuCC: + case IROp::FCmpVfpuBit: + case IROp::FCmpVfpuAggregate: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FCondAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FMin: + case IROp::FMax: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FCvt(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FCvtWS: + case IROp::FCvtSW: + case IROp::FCvtScaledWS: + case IROp::FCvtScaledSW: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FRound(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FRound: + case IROp::FTrunc: + case IROp::FCeil: + case IROp::FFloor: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FSat(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FSat0_1: + case IROp::FSatMinus1_1: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FSpecial(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FSin: + case IROp::FCos: + case IROp::FRSqrt: + case IROp::FRecip: + case IROp::FAsin: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_RoundingMode(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::RestoreRoundingMode: + RestoreRoundingMode(); + break; + + case IROp::ApplyRoundingMode: + ApplyRoundingMode(); + break; + + case IROp::UpdateRoundingMode: + // TODO: We might want to do something here? + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRCompLoadStore.cpp b/Core/MIPS/x86/X64IRCompLoadStore.cpp new file mode 100644 index 0000000000..d80e5c40cb --- /dev/null +++ b/Core/MIPS/x86/X64IRCompLoadStore.cpp @@ -0,0 +1,179 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include "Core/MemMap.h" +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for load/store instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_CondStore(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Store32Conditional: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FLoad(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::LoadFloat: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_FStore(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::StoreFloat: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Load(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Load8: + case IROp::Load8Ext: + case IROp::Load16: + case IROp::Load16Ext: + case IROp::Load32: + case IROp::Load32Linked: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_LoadShift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Load32Left: + case IROp::Load32Right: + // Should not happen if the pass to split is active. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Store(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Store8: + case IROp::Store16: + case IROp::Store32: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_StoreShift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Store32Left: + case IROp::Store32Right: + // Should not happen if the pass to split is active. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecLoad(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::LoadVec4: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecStore(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::StoreVec4: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRCompSystem.cpp b/Core/MIPS/x86/X64IRCompSystem.cpp new file mode 100644 index 0000000000..5ff96d0c86 --- /dev/null +++ b/Core/MIPS/x86/X64IRCompSystem.cpp @@ -0,0 +1,142 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include "Common/Profiler/Profiler.h" +#include "Core/Core.h" +#include "Core/HLE/HLE.h" +#include "Core/HLE/ReplaceTables.h" +#include "Core/MemMap.h" +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_Basic(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Downcount: + //ADD(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG), Imm32(-(s32)inst.constant)); + SUB(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32((s32)inst.constant)); + break; + + case IROp::SetConst: + regs_.SetGPRImm(inst.dest, inst.constant); + break; + + case IROp::SetConstF: + case IROp::SetPC: + case IROp::SetPCConst: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Breakpoint(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Breakpoint: + case IROp::MemoryCheck: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_System(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Syscall: + case IROp::CallReplacement: + case IROp::Break: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_Transfer(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::SetCtrlVFPU: + case IROp::SetCtrlVFPUReg: + case IROp::SetCtrlVFPUFReg: + case IROp::FpCondFromReg: + case IROp::FpCondToReg: + case IROp::FpCtrlFromReg: + case IROp::FpCtrlToReg: + case IROp::VfpuCtrlToReg: + case IROp::FMovFromGPR: + case IROp::FMovToGPR: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_ValidateAddress(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ValidateAddress8: + case IROp::ValidateAddress16: + case IROp::ValidateAddress32: + case IROp::ValidateAddress128: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRCompVec.cpp b/Core/MIPS/x86/X64IRCompVec.cpp new file mode 100644 index 0000000000..051c8c0fd7 --- /dev/null +++ b/Core/MIPS/x86/X64IRCompVec.cpp @@ -0,0 +1,130 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "ppsspp_config.h" +#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) + +#include +#include "Core/MemMap.h" +#include "Core/MIPS/x86/X64IRJit.h" +#include "Core/MIPS/x86/X64IRRegCache.h" + +// This file contains compilation for vector instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace Gen; +using namespace X64IRJitConstants; + +void X64JitBackend::CompIR_VecArith(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Add: + case IROp::Vec4Sub: + case IROp::Vec4Mul: + case IROp::Vec4Div: + case IROp::Vec4Scale: + case IROp::Vec4Neg: + case IROp::Vec4Abs: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Init: + case IROp::Vec4Shuffle: + case IROp::Vec4Blend: + case IROp::Vec4Mov: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecClamp(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4ClampToZero: + case IROp::Vec2ClampToZero: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecHoriz(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Dot: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void X64JitBackend::CompIR_VecPack(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec2Unpack16To31: + case IROp::Vec4Pack32To8: + case IROp::Vec2Pack31To16: + case IROp::Vec4Unpack8To32: + case IROp::Vec2Unpack16To32: + case IROp::Vec4DuplicateUpperBitsAndShift1: + case IROp::Vec4Pack31To8: + case IROp::Vec2Pack32To16: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp + +#endif diff --git a/Core/MIPS/x86/X64IRJit.cpp b/Core/MIPS/x86/X64IRJit.cpp index 7d7c90b6a0..54f5e4c7b2 100644 --- a/Core/MIPS/x86/X64IRJit.cpp +++ b/Core/MIPS/x86/X64IRJit.cpp @@ -325,48 +325,6 @@ void X64JitBackend::LoadStaticRegisters() { } } -// TODO: Move out to files. -void X64JitBackend::CompIR_Arith(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Assign(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Basic(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Bits(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Breakpoint(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Compare(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_CondAssign(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_CondStore(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Div(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Exit(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_ExitIf(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FArith(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FAssign(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FCompare(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FCondAssign(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FCvt(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FLoad(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FRound(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FSat(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FSpecial(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_FStore(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_HiLo(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Load(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_LoadShift(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Logic(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Mult(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_RoundingMode(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Shift(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Store(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_StoreShift(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_System(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_Transfer(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecArith(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecAssign(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecClamp(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecHoriz(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecLoad(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecPack(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_VecStore(IRInst inst) { CompIR_Generic(inst); } -void X64JitBackend::CompIR_ValidateAddress(IRInst inst) { CompIR_Generic(inst); } - } // namespace MIPSComp #endif diff --git a/UWP/CoreUWP/CoreUWP.vcxproj b/UWP/CoreUWP/CoreUWP.vcxproj index a2914b2615..9120724fc7 100644 --- a/UWP/CoreUWP/CoreUWP.vcxproj +++ b/UWP/CoreUWP/CoreUWP.vcxproj @@ -576,6 +576,12 @@ + + + + + + diff --git a/UWP/CoreUWP/CoreUWP.vcxproj.filters b/UWP/CoreUWP/CoreUWP.vcxproj.filters index 58215c1e3d..91839d6316 100644 --- a/UWP/CoreUWP/CoreUWP.vcxproj.filters +++ b/UWP/CoreUWP/CoreUWP.vcxproj.filters @@ -192,6 +192,24 @@ MIPS\x86 + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + + + MIPS\x86 + MIPS\x86 diff --git a/android/jni/Android.mk b/android/jni/Android.mk index 371872c544..95e98a34fb 100644 --- a/android/jni/Android.mk +++ b/android/jni/Android.mk @@ -304,6 +304,12 @@ ARCH_FILES := \ $(SRC)/Core/MIPS/x86/RegCache.cpp \ $(SRC)/Core/MIPS/x86/RegCacheFPU.cpp \ $(SRC)/Core/MIPS/x86/X64IRAsm.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompALU.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompBranch.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompFPU.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompLoadStore.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompSystem.cpp \ + $(SRC)/Core/MIPS/x86/X64IRCompVec.cpp \ $(SRC)/Core/MIPS/x86/X64IRJit.cpp \ $(SRC)/Core/MIPS/x86/X64IRRegCache.cpp \ $(SRC)/GPU/Common/VertexDecoderX86.cpp \ diff --git a/libretro/Makefile.common b/libretro/Makefile.common index 020c2652d2..f7c2c98a29 100644 --- a/libretro/Makefile.common +++ b/libretro/Makefile.common @@ -803,6 +803,12 @@ ifeq ($(WITH_DYNAREC),1) $(COREDIR)/MIPS/x86/RegCache.cpp \ $(COREDIR)/MIPS/x86/RegCacheFPU.cpp \ $(COREDIR)/MIPS/x86/X64IRAsm.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompALU.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompBranch.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompFPU.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompLoadStore.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompSystem.cpp \ + $(COREDIR)/MIPS/x86/X64IRCompVec.cpp \ $(COREDIR)/MIPS/x86/X64IRJit.cpp \ $(COREDIR)/MIPS/x86/X64IRRegCache.cpp \ $(GPUDIR)/Common/VertexDecoderX86.cpp