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riscv: Fix load error w/o pointerify.
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commit
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1 file changed
+2
-5
@@ -80,11 +80,8 @@ void RiscVJitBackend::CompIR_Load(IRInst inst) {
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SetScratch1ToSrc1Address(inst.src1);
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addrReg = SCRATCH1;
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}
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// If they're the same, MapReg may subtract MEMBASEREG, so just mark dirty.
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if (inst.dest == inst.src1)
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gpr.MarkDirty(gpr.R(inst.dest), true);
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else
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gpr.MapReg(inst.dest, MIPSMap::NOINIT | MIPSMap::MARK_NORM32);
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// With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1.
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gpr.MapReg(inst.dest, MIPSMap::NOINIT | MIPSMap::MARK_NORM32);
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gpr.ReleaseSpillLock(inst.dest, inst.src1);
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s32 imm = AdjustForAddressOffset(&addrReg, inst.constant);
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