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3004 Commits
Author SHA1 Message Date
Unknown W. Brackets b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
Unknown W. Brackets 18c48681a8 riscv: Implement multiply instructions. 2023-07-23 18:01:50 -07:00
Unknown W. Brackets 7f4689e8fa riscv: Use direct SLI/SLIU instructions. 
Derp, I forgot these existed on RISC-V for a moment.
 2023-07-23 18:01:46 -07:00
Unknown W. Brackets 4100767b5e riscv: Optimize SetConst a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets f7f7531500 riscv: Fix min/max normalization. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 34bfe93ea5 riscv: Fix block lookup issues. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 92694e765f riscv: Implement conditional moves. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 5ed2f0d559 riscv: Implement logic ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 7aafa11d24 riscv: Implement conditional exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 720f868a10 riscv: Use R_RA as a temporary for calls. 
This is the most logical thing, since we're about to write it anyway.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 76e3246065 riscv: Reduce jit codesize a bit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 624caa2dea riscv: Implement the simplest exits. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 1dfedde741 riscv: Avoid needless save/load around compile. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 165169eb31 riscv: Implement load and store ops. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets c2da7d18bb riscv: Stub out more IR compilation categories. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 05a2789cf4 riscv: Implement some simple assign instructions. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets c6c25af484 riscv: Add some safety to pointerifying. 
We have to clear the upper bits in case of sign extension or other things.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets bf7a6eb2cd riscv: Add jit for some initial instructions. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets b2d3c750f1 irjit: Define a specific IRReg type. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e271e43ec5 riscv: Initial staffolding for IR based jit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 3468423bb4 Debugger: Handle missing crash/block ptrs better. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e4f9c72fe9 riscv: Avoid unaligned mem combine in IR. 2023-07-16 16:20:58 -07:00
Unknown W. Brackets d4e689b096 irjit: Allow IRInterpret() on partial block. 
For later if we want to fallback from native to IR interpret.
 2023-07-16 16:19:53 -07:00
Henrik Rydgård 4a4cd3d977 Add logging when loading a save state that has "unknown-prefix-mode" set 2023-06-14 10:23:23 +02:00
fp64 dcaca7f111 Fix vrnd to the current understanding 
Followup to #17506.
 2023-06-04 16:44:27 -04:00
Unknown W. BracketsandGitHub f54f5581cd interp: Potential linker buildfix. 
Just in case it's thinking there's a definition to link, should use static.
 2023-06-04 19:23:16 -07:00
Henrik Rydgård 1ef1478cc8 Remove more impossibilities (GetMtxSize) 2023-06-04 11:48:43 +02:00
Henrik Rydgård a92cca2575 Don't check for impossibilities. Minor speedup for GetVecSize. 2023-06-04 11:28:39 +02:00
Henrik Rydgård 9db9fec898 VFPU: Some micro-optimizations. Don't fall back to interpreter path for vexp/vlog/vrexp. 2023-06-04 11:28:33 +02:00
fp64 a97c911d46 Address feedback 2023-05-25 17:28:38 -04:00
fp64 23ef21ba9b Fix a bug, and bump savestate version 2023-05-25 16:18:58 -04:00
fp64 71884d5843 Make vrnd match HW closer 
See investigation starting
https://github.com/hrydgard/ppsspp/issues/16946#issuecomment-1467261209
for more details.
Still needs more testing.
 2023-05-25 14:18:19 -04:00
Henrik RydgårdandGitHub 67a35d3476 Merge pull request #17356 from unknownbrackets/minor-cleanup 
Cleanup some more string formats, mostly in debugger
 2023-05-23 08:29:23 +02:00
Henrik RydgårdandGitHub 13815e6f5a Merge pull request #17423 from unknownbrackets/debugger 
Debugger: Correct PC if replacement breaks
 2023-05-06 23:08:53 +02:00
Unknown W. Brackets 87217053ef Debugger: Correct PC if replacement breaks. 
If a memory breakpoint hits within a replacement (like memcpy, memset) we
would previously move PC back to the jal in cases, which would break
things if you tried to resume.
 2023-05-06 13:40:01 -07:00
Henrik Rydgård 4e732af786 Minor cleanup, add a speculative comment. 2023-05-04 10:07:49 +02:00
Henrik Rydgård 1a2d599942 JIT: Consider the block cache full a few block before it is, to allow space for proxy blocks. 
Should fix the following crash:

Core/MIPS/JitCommon/JitBlockCache.cpp:190

JitBlock &b = blocks_[num_blocks_];
 2023-05-02 21:53:01 +02:00
Unknown W. Brackets 07d2b77c2a Debugger: Add a simple way to exclude from hashmap. 
Sometimes funcs have common patterns, this is a quick way to avoid
poisoning the hashmap.
 2023-04-29 10:59:32 -07:00
Unknown W. Brackets 5b1235537f Debugger: Make disasm more thread safe. 2023-04-29 09:56:17 -07:00
Unknown W. Brackets 6da10463f9 Debugger: Make reg names safer, stop using v000. 
Better to use S000, etc. as that's more clear throughout.
 2023-04-29 09:48:33 -07:00
Unknown W. Brackets 2f3a0ea0b5 Debugger: Simplify expression error handling. 2023-04-29 09:15:14 -07:00
Unknown W. Brackets 46101581c0 Core: Cleanup disasm buffer usage. 2023-04-29 09:07:25 -07:00
Henrik Rydgård 7723aebb9b Buildfixes 2023-04-28 21:56:39 +02:00