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Debugger: Make disasm more thread safe.

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2023-04-29 09:56:17 -07:00
parent 6da10463f9
commit 5b1235537f
9 changed files with 24 additions and 25 deletions
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Core/MIPS/ARM/ArmCompVFPU.cpp
+1 -1
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@@ -142,7 +142,7 @@ namespace MIPSComp
// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
// TODO: But some ops seem to use const 0 instead?
if (regnum >= n) {
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC()));
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC()).c_str());
regnum = 0;
}
Core/MIPS/ARM/ArmRegCacheFPU.cpp
+3 -3
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@@ -584,11 +584,11 @@ ARMReg ArmRegCacheFPU::R(int mipsReg) {
return (ARMReg)(mr[mipsReg].reg + S0);
} else {
if (mipsReg < 32) {
ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
} else if (mipsReg < 32 + 128) {
ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
} else {
ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
}
return INVALID_REG; // BAAAD
}
Core/MIPS/ARM64/Arm64CompVFPU.cpp
+1 -1
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@@ -134,7 +134,7 @@ namespace MIPSComp {
// Prefix may say "z, z, z, z" but if this is a pair, we force to x.
// TODO: But some ops seem to use const 0 instead?
if (regnum >= n) {
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC()));
WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC()).c_str());
regnum = 0;
}
Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
+3 -3
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@@ -520,11 +520,11 @@ ARM64Reg Arm64RegCacheFPU::R(int mipsReg) {
return (ARM64Reg)(mr[mipsReg].reg + S0);
} else {
if (mipsReg < 32) {
ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "FReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
} else if (mipsReg < 32 + 128) {
ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "VReg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
} else {
ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC));
ERROR_LOG(JIT, "Tempreg %i not in ARM reg. compilerPC = %08x : %s", mipsReg - 128 - 32, js_->compilerPC, MIPSDisasmAt(js_->compilerPC).c_str());
}
return INVALID_REG; // BAAAD
}
Core/MIPS/MIPSDis.cpp
+7 -9
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@@ -40,10 +40,8 @@
namespace MIPSDis
{
// One shot, not re-entrant.
const char *SignedHex(int i)
{
static char temp[32];
std::string SignedHex(int i) {
char temp[32];
int offset = 0;
if (i < 0)
{
@@ -64,7 +62,7 @@ namespace MIPSDis
int imm = SignExtend16ToS32(op & 0xFFFF);
int rs = _RS;
int func = (op >> 16) & 0x1F;
snprintf(out, outSize, "%s\tfunc=%i, %s(%s)", MIPSGetName(op), func, RN(rs), SignedHex(imm));
snprintf(out, outSize, "%s\tfunc=%i, %s(%s)", MIPSGetName(op), func, RN(rs), SignedHex(imm).c_str());
}
void Dis_mxc1(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
@@ -94,7 +92,7 @@ namespace MIPSDis
int ft = _FT;
int rs = _RS;
const char *name = MIPSGetName(op);
snprintf(out, outSize, "%s\t%s, %s(%s)", name, FN(ft), SignedHex(offset), RN(rs));
snprintf(out, outSize, "%s\t%s, %s(%s)", name, FN(ft), SignedHex(offset).c_str(), RN(rs));
}
void Dis_FPUComp(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
@@ -170,7 +168,7 @@ namespace MIPSDis
case 8: //addi
case 9: //addiu
case 10: //slti
snprintf(out, outSize, "%s\t%s, %s, %s", name, RN(rt), RN(rs), SignedHex(simm));
snprintf(out, outSize, "%s\t%s, %s, %s", name, RN(rt), RN(rs), SignedHex(simm).c_str());
break;
case 11: //sltiu
snprintf(out, outSize, "%s\t%s, %s, 0x%X", name, RN(rt), RN(rs), suimm);
@@ -203,7 +201,7 @@ namespace MIPSDis
int rt = _RT;
int rs = _RS;
if (rs == 0)
snprintf(out, outSize, "li\t%s, %s", RN(rt), SignedHex(imm));
snprintf(out, outSize, "li\t%s, %s", RN(rt), SignedHex(imm).c_str());
else
Dis_IType(op, pc, out, outSize);
}
@@ -213,7 +211,7 @@ namespace MIPSDis
int rt = _RT;
int rs = _RS;
const char *name = MIPSGetName(op);
snprintf(out, outSize, "%s\t%s, %s(%s)", name, RN(rt), SignedHex(imm), RN(rs));
snprintf(out, outSize, "%s\t%s, %s(%s)", name, RN(rt), SignedHex(imm).c_str(), RN(rs));
}
void Dis_RType2(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
Core/MIPS/MIPSDisVFPU.cpp
+4 -4
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@@ -100,14 +100,14 @@ inline const char *VSuff(MIPSOpcode op)
namespace MIPSDis
{
const char *SignedHex(int i);
std::string SignedHex(int i);
void Dis_SV(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
int offset = SignExtend16ToS32(op & 0xFFFC);
int vt = ((op>>16)&0x1f)|((op&3)<<5);
int rs = (op>>21) & 0x1f;
const char *name = MIPSGetName(op);
snprintf(out, outSize, "%s\t%s, %s(%s)", name, VN(vt, V_Single), SignedHex(offset), RN(rs));
snprintf(out, outSize, "%s\t%s, %s(%s)", name, VN(vt, V_Single), SignedHex(offset).c_str(), RN(rs));
}
void Dis_SVQ(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
@@ -116,7 +116,7 @@ namespace MIPSDis
int rs = (op>>21) & 0x1f;
const char *name = MIPSGetName(op);
size_t outpos = 0;
outpos += snprintf(out, outSize, "%s\t%s, %s(%s)", name, VN(vt, V_Quad), SignedHex(offset), RN(rs));
outpos += snprintf(out, outSize, "%s\t%s, %s(%s)", name, VN(vt, V_Quad), SignedHex(offset).c_str(), RN(rs));
if ((op & 2) && outpos < outSize)
truncate_cpy(out + outpos, outSize - outpos, ", wb");
}
@@ -127,7 +127,7 @@ namespace MIPSDis
int rs = (op>>21) & 0x1f;
int lr = (op>>1)&1;
const char *name = MIPSGetName(op);
snprintf(out, outSize, "%s%s.q\t%s, %s(%s)", name, lr ? "r" : "l", VN(vt, V_Quad), SignedHex(offset), RN(rs));
snprintf(out, outSize, "%s%s.q\t%s, %s(%s)", name, lr ? "r" : "l", VN(vt, V_Quad), SignedHex(offset).c_str(), RN(rs));
}
void Dis_Mftv(MIPSOpcode op, uint32_t pc, char *out, size_t outSize) {
Core/MIPS/MIPSIntVFPU.cpp
+1 -1
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@@ -124,7 +124,7 @@ void ApplyPrefixST(float *r, u32 data, VectorSize size, float invalid = 0.0f) {
if (!constants) {
if (regnum >= n) {
// We mostly handle this now, but still worth reporting.
ERROR_LOG_REPORT(CPU, "Invalid VFPU swizzle: %08x: %i / %d at PC = %08x (%s)", data, regnum, n, currentMIPS->pc, MIPSDisasmAt(currentMIPS->pc));
ERROR_LOG_REPORT(CPU, "Invalid VFPU swizzle: %08x: %i / %d at PC = %08x (%s)", data, regnum, n, currentMIPS->pc, MIPSDisasmAt(currentMIPS->pc).c_str());
}
r[i] = origV[regnum];
if (abs)
Core/MIPS/MIPSTables.cpp
+2 -2
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@@ -1119,8 +1119,8 @@ int MIPSGetMemoryAccessSize(MIPSOpcode op) {
return 0;
}
const char *MIPSDisasmAt(u32 compilerPC) {
static char temp[256];
std::string MIPSDisasmAt(u32 compilerPC) {
char temp[512];
MIPSDisAsm(Memory::Read_Instruction(compilerPC), 0, temp, sizeof(temp));
return temp;
}
Core/MIPS/MIPSTables.h
+2 -1
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@@ -17,6 +17,7 @@
#pragma once
#include <string>
#include "Common/CommonTypes.h"
#include "Core/MIPS/MIPS.h"
@@ -132,4 +133,4 @@ MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op);
int MIPSGetInstructionCycleEstimate(MIPSOpcode op);
int MIPSGetMemoryAccessSize(MIPSOpcode op);
const char *MIPSGetName(MIPSOpcode op);
const char *MIPSDisasmAt(u32 compilerPC);
std::string MIPSDisasmAt(u32 compilerPC);