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522 Commits
Author SHA1 Message Date
Unknown W. Brackets 9157d992ac jit-ir: Implement cfc1/ctc1. 
This makes it so we can track rounding mode changes.
 2023-07-25 20:33:56 -07:00
Unknown W. Brackets 05360d5c7a riscv: Implement simplest float ops. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets a8edf5fa24 riscv: Reduce bloat in jit fallbacks. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets b2d3c750f1 irjit: Define a specific IRReg type. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e271e43ec5 riscv: Initial staffolding for IR based jit. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets 3468423bb4 Debugger: Handle missing crash/block ptrs better. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets e4f9c72fe9 riscv: Avoid unaligned mem combine in IR. 2023-07-16 16:20:58 -07:00
Unknown W. Brackets d4e689b096 irjit: Allow IRInterpret() on partial block. 
For later if we want to fallback from native to IR interpret.
 2023-07-16 16:19:53 -07:00
Unknown W. Brackets 6da10463f9 Debugger: Make reg names safer, stop using v000. 
Better to use S000, etc. as that's more clear throughout.
 2023-04-29 09:48:33 -07:00
Unknown W. Brackets 46101581c0 Core: Cleanup disasm buffer usage. 2023-04-29 09:07:25 -07:00
Henrik Rydgård fc62d587c0 Fix whitespace issues 2023-04-02 16:36:39 +02:00
Герман СеменовandHenrik Rydgård 8d5af48efd Core: using if constexpr C++17 optimization 2023-04-02 16:35:57 +02:00
Henrik Rydgård d586ec0d5e Don't create Host objects except in headless/unittest 2023-03-25 10:47:01 +01:00
Unknown W. Brackets d97790e28e irjit: Fix vi2us/vi2s with non-consecutive. 
Vec2ClampToZero and similar assume consecutive.
 2023-03-15 21:30:35 -07:00
Henrik Rydgård 700a018ef0 IRInterpreter: Use alignment as access size in exceptions 2023-01-01 20:48:16 +01:00
Henrik Rydgård aa80659530 Memory exception: Add facility to track size 
Might theoretically help in tracking some things down.

Not fully utilized yet, the fault handler needs to extract the
information from the faulting instruction. But we can use it for
GetPointerRange etc.
 2023-01-01 20:30:29 +01:00
Unknown W. Brackets 9cfcbc46e6 Global: Cleanup initialization/pointer checks. 
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets a7b7bf7826 Global: Set many read-only params as const. 
This makes what they do and which args to use clearer, if nothing else.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets f44852bb18 Global: Cleanup virtual/override specifiers. 
Also missing virtual destructors, hidden non-overrides, etc.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets 2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Henrik RydgårdandGitHub e97d5498c6 Merge pull request #16306 from unknownbrackets/ir-prefixes 
irjit: Correct prefix validation
 2022-10-31 09:11:52 +01:00
Unknown W. Brackets eef29d5e95 irjit: Correct prefix validation. 
Some vcmps, etc. were perfectly valid but were forcing to interp.
This also catches more cases that should go to interp correctly.
 2022-10-30 23:15:54 -07:00
Unknown W. Brackets 56ff555309 irjit: Fix unordered float compares. 2022-10-30 21:12:59 -07:00
Unknown W. Brackets bbdc8a8f98 interp: Correct vscl/vmscl t prefix handling. 
This makes more sense.  Fixes Dissidia 012 issues.
 2022-10-29 22:43:30 -07:00
Unknown W. Brackets 3f997518f3 irjit: Handle vrot overlap more correctly. 
Sine ignores overlap, cosine does not.
 2022-10-29 22:25:25 -07:00
Unknown W. Brackets bac36df453 x86jit: Refactor and fix jump in branch delay slot. 
This seems cleaner, instead of the duplication of lines for each branch
type.
 2022-09-03 19:58:46 -07:00
Unknown W. Brackets d08ee44cf4 irjit: Handle branch/jump in branch delay slots. 
See #15952 for more detail.
 2022-09-03 19:05:31 -07:00
Unknown W. Brackets 8e7847f6d9 UI: Show return address for exec crashes. 2022-08-21 14:49:34 -07:00
Unknown W. Brackets 80e481bbdc Core: Show exception on misaligned jump. 2022-08-21 14:49:34 -07:00
Unknown W. Brackets 90517ace59 irjit: Validate alignment in slow memory mode. 2022-08-21 13:24:10 -07:00
Unknown W. Brackets 6715f41410 irjit: Add constructs for validing mem access. 
Basically to allow slow/fast memory to work with IR, including for
alignment checks.
 2022-08-21 13:01:23 -07:00
Unknown W. Brackets 7b081a61c8 irjit: Correct another PurgeTemps case. 
In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.
 2022-07-27 19:38:16 -07:00
Unknown W. Brackets 5abf1362a2 irjit: Clarify PurgeTemps, guard a couple ops. 
Although I think we skip simplify passes on breakpoints entirely, safer to
exclude these ops.
 2022-07-27 19:36:53 -07:00
Unknown W. Brackets 2154f747fc irjit: Simplify more arithmetic to Movs. 
Later passes rely on things being Mov, so better to have them more often.
 2022-07-24 11:35:54 -07:00
Unknown W. Brackets 8f23025209 irjit: Add tests for IR passes. 2022-07-24 11:35:54 -07:00
Unknown W. Brackets c2a1caa2a2 irjit: Prevent corruption on purge temps pass. 
If a switch occurs and then something clobbers the dest of that switch, we
were wiping out the first of those three instructions incorrectly.
 2022-07-21 09:06:37 -07:00
Unknown W. Brackets 25e18195ce irjit: Allow unaligned loads by default. 
This was the original intention, was a mistake that this was flipped.
 2022-07-11 17:36:39 -07:00
Henrik Rydgård cd92151de7 Add ARM64_NEON compile arch flag 
This allows doing ARM64 builds without NEON support, and allows simplifying some checks.
 2022-06-25 07:29:20 +02:00
Unknown W. Brackets 2479d52202 Global: Reduce includes of common headers. 
In many places, string, map, or Common.h were included but not needed.
 2022-01-30 16:35:33 -08:00
Unknown W. Brackets bc16a55028 jit: Count delay slot cycles separately. 
This makes it easier to count cycles per instruction, instead of ignoring
the delay slot's instruction for cycle count.
 2021-04-12 07:04:22 -07:00
Unknown W. Brackets cae0815095 jit: Avoid using mips identifier directly. 
Apparently this gets defined on mips systems.
 2021-02-26 07:24:58 -08:00
Unknown W. Brackets f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Unknown W. Brackets 5d60fa0d0d Common: Maintain C++11 support in sign extend. 2021-01-31 08:44:02 -08:00
Unknown W. Brackets 1b00da2f3a Common: Sign extend w/func not chained casts. 
Should be clearer to read and easier to get right.
 2021-01-31 01:25:52 -08:00
Unknown W. Brackets e99c69f19e jit: Be very clear on sign extension. 2021-01-30 11:41:30 -08:00
Unknown W. Brackets c179cad5c2 jit: Make branch shift more obvious. 
And also not technically undefined behavior.
 2021-01-29 20:53:41 -08:00
Unknown W. Brackets 5354459476 irjit: Update clobber flag on inst swap. 
Fixes IR in Persona 3.
 2021-01-10 16:41:45 -08:00
Unknown W. Brackets 9dcb70d502 irjit: Add disable flag for simplify passes. 2021-01-10 14:50:32 -08:00