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irjit: Fix vi2us/vi2s with non-consecutive.

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Vec2ClampToZero and similar assume consecutive.
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Unknown W. Brackets committed 2023-03-15 21:30:35 -07:00
1 parent fa1a4d26dc
commit d97790e28e
1 file changed
+7 -3
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Core/MIPS/IR/IRCompVFPU.cpp
+7 -3
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@@ -72,6 +72,10 @@ namespace MIPSComp {
regs[3] == regs[2] + 1;
}
static bool IsVec2(VectorSize sz, const u8 regs[2]) {
return sz == V_Pair && IsConsecutive2(regs) && (regs[0] & 1) == 0;
}
static bool IsVec4(VectorSize sz, const u8 regs[4]) {
return sz == V_Quad && IsConsecutive4(regs) && (regs[0] & 3) == 0;
}
@@ -1534,10 +1538,10 @@ namespace MIPSComp {
int nOut = GetNumVectorElements(outsize);
// If src registers aren't contiguous, make them (mainly for bits == 8.)
if (sz == V_Quad && !IsVec4(sz, sregs)) {
// If src registers aren't contiguous, make them.
if (!IsVec2(sz, sregs) && !IsVec4(sz, sregs)) {
// T prefix is unused.
for (int i = 0; i < 4; i++) {
for (int i = 0; i < GetNumVectorElements(sz); i++) {
srcregs[i] = IRVTEMP_PFX_T + i;
ir.Write(IROp::FMov, srcregs[i], sregs[i]);
}