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522 Commits
Author SHA1 Message Date
Unknown W. Brackets 09e307b097 arm64jit: Update rounding mode on thread switch. 
Since fcr31 is per-thread, we must update jit state when it changes.
This also fixes the rounding mode on load state and jit/interp switch.
 2018-04-01 10:12:32 -07:00
Henrik Rydgård 34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård fb0e81484b Minor cleanup 2018-01-10 09:19:27 +01:00
Henrik RydgårdandGitHub 4a32ec3102 Merge pull request #10516 from unknownbrackets/irjit-lwr 
irjit: Optimize out more temps and lwl/lwr operations
 2018-01-10 09:11:10 +01:00
Unknown W. Brackets b6bb0159e3 irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
Unknown W. Brackets f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
Unknown W. Brackets fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
Unknown W. Brackets d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
Unknown W. Brackets b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
Unknown W. Brackets c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
Unknown W. Brackets 6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
Unknown W. Brackets cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
Unknown W. Brackets 97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
Unknown W. Brackets cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00
Unknown W. Brackets 463b2a90c7 irjit: Allow precompiling funcs at start. 
This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.

This is basically the same operation as loading from cache, without the
cache yet.
 2018-01-06 17:06:53 -08:00
Unknown W. Brackets ccd562d934 irjit: Add a safety check for block num overflow. 
In case a game is very frequently modifying some block.
 2018-01-04 23:24:15 -08:00
Unknown W. Brackets 0bfab27b46 irjit: Calculate bloat statistics. 
At least based on IR for now.  Can do something else later.

memset() was causing a crash on the std::map.
 2018-01-04 23:09:03 -08:00
Henrik RydgårdandGitHub 2709472abd Merge pull request #10506 from hrydgard/ir-interpreter-simd 
More IR interpreter SIMD
 2018-01-05 01:21:32 +01:00
Henrik RydgårdandGitHub 8c3a50d089 Merge pull request #10505 from hrydgard/ir-disasm-jit-compare 
Show IR disassembly in JIT Compare screen
 2018-01-05 01:20:49 +01:00
Henrik Rydgård d1d01bfdcb Cleanup GetBlockNumberFromStartAddress 2018-01-05 01:20:10 +01:00
Henrik Rydgård 331a8f91e8 Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
Henrik Rydgård 18be23eccc IR: More fixes. Still something wrong with VFPU compares (not caused by this PR). 2018-01-04 19:38:36 +01:00
Henrik Rydgård ca9050b84c On Linux, can't even include nmmintrin without explicitly enabling SSE 4.2 support. 2018-01-04 18:27:19 +01:00
Henrik Rydgård fe88d12055 IR interpreter: Add some braces to allow variable declaration in the switch cases. 2018-01-04 18:27:19 +01:00
Henrik Rydgård e0cc126d09 Add some more SIMD support to IR interpreter. Mostly just because, but also serves as implementation reference for later code generation backends. 2018-01-04 18:27:19 +01:00
Henrik Rydgård a128624f98 IRInterpreter: Fix bugs in floating point truncation functions 2018-01-04 18:25:54 +01:00
Henrik Rydgård 1a97f62dc9 Fix running the CPU test from the UI. 2018-01-04 18:10:41 +01:00
Henrik Rydgård 468b830bec Show IR disassembly in JIT Compare screen 2018-01-04 12:23:23 +01:00
Henrik Rydgård 604b3c3e97 IR Interpreter: Add missing break; to switch case IROp::FSign. 2018-01-04 11:08:56 +01:00
Unknown W. Brackets bc541bd020 irjit: Encode downcount directly as a constant. 
Simpler this way, now.
 2018-01-03 23:32:31 -08:00
Unknown W. Brackets cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Unknown W. Brackets 64b57a0329 irjit: Fix swr typo. 
Shifting the wrong direction - oops.
 2018-01-03 08:14:25 -08:00
Henrik Rydgård 3ac2350ad6 IR Interpreter: Add a comment, minor cleanup, minor SSE stuff. 2018-01-03 16:31:55 +01:00
Unknown W. Brackets b11858d9a0 irjit: Properly account for delay slots in size. 
Otherwise we think blocks are 4 bytes too short, which can affect
invalidation.
 2018-01-01 22:54:40 -08:00
Unknown W. Brackets 3abcc4d6d8 irjit: Implement lwl/lwr/swl/swr. 
This is very similar to the arm64jit implementation.
 2018-01-01 08:38:13 -08:00
Unknown W. Brackets b37ba9e599 irjit: Add options for compile/optimize steps. 
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
 2018-01-01 08:38:12 -08:00
Unknown W. Brackets 671be24105 irjit: Add extra temps to make lwl/swl/etc. easier. 2018-01-01 08:38:11 -08:00
Unknown W. Brackets 905d2c2da6 irjit: Cleanup some invalid op handling. 
And log blocks the same way as other backends.
 2018-01-01 08:38:11 -08:00
Unknown W. Brackets 8ffb0101fe jit: Report blocks with uneaten VFPU prefixes. 
There may be options to avoid, like continuing these blocks, especially if
they're likely or something.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets 3af78883c7 irjit: Speed up icache block invalidation. 
Turns out, in games using a ton of small memcpys, this was causing perf
issues.
 2017-12-31 10:37:09 -08:00
Unknown W. Brackets 8c2edd432b irjit: Allow continuing from mips break. 
Some games currently generate break instructions, and can be played
otherwise.  Should be fixed, but let's not hard crash.
 2017-12-25 10:21:22 -08:00
Henrik Rydgård 0207739d76 Can't call functions through known-nil pointers, even if they don't touch local data - LLVM's optimizer might have done something stupid. 2017-11-30 01:07:03 +01:00
Henrik Rydgård 22e65ba80d Get rid of ugly alignment macros and some other cruft, we now have alignas(16) from C++11 2017-08-31 01:14:51 +02:00
Unknown W. Brackets 33b073c545 Jit: Fix syscall outside delay slot. 
Doesn't happen in real games, but useful in debug code.
 2017-06-04 10:39:01 -07:00
Unknown W. Brackets b483444fab IR: Cleanup some invalid ops. 2017-04-20 21:11:40 -07:00
Henrik Rydgard b0bd7e3c6f Minor changes for compatibility with VS2017 2017-03-12 17:33:00 +01:00
Henrik Rydgård 635b2ada43 Remove a function that didn't make a lot of sense. 2017-01-26 09:50:16 +01:00
Henrik Rydgard 5d5f10d956 Attempts to counter crashes seen in the Google Play developer console 2016-12-01 22:07:03 +01:00
Florent Castelli 4145b60a0e symbian: Remove! 2016-10-11 18:49:08 +02:00
Henrik RydgårdandGitHub ea6b72d4c9 Merge pull request #8888 from unknownbrackets/warnings 
Warning fixes
 2016-08-06 10:59:06 +02:00