Unknown W. Brackets 8ffb0101fe jit: Report blocks with uneaten VFPU prefixes. ...

There may be options to avoid, like continuing these blocks, especially if
they're likely or something.

2018-01-01 08:38:10 -08:00

..

IRAsm.cpp

Initial commit for IRJit

2016-05-07 13:58:29 +02:00

IRCompALU.cpp

jit-ir: Add div/divu instructions.

2016-05-14 19:23:52 -07:00

IRCompBranch.cpp

Jit: Fix syscall outside delay slot.

2017-06-04 10:39:01 -07:00

IRCompFPU.cpp

jit-ir: Implement memory breakpoints.

2016-07-02 16:38:30 -07:00

IRCompLoadStore.cpp

jit-ir: Implement memory breakpoints.

2016-07-02 16:38:30 -07:00

IRCompVFPU.cpp

Get rid of ugly alignment macros and some other cruft, we now have alignas(16) from C++11

2017-08-31 01:14:51 +02:00

IRFrontend.cpp

jit: Report blocks with uneaten VFPU prefixes.

2018-01-01 08:38:10 -08:00

IRFrontend.h

jit: Report blocks with uneaten VFPU prefixes.

2018-01-01 08:38:10 -08:00

IRInst.cpp

jit-ir: Implement memory breakpoints.

2016-07-02 16:38:30 -07:00

IRInst.h

symbian: Remove!

2016-10-11 18:49:08 +02:00

IRInterpreter.cpp

irjit: Allow continuing from mips break.

2017-12-25 10:21:22 -08:00

IRInterpreter.h

jit-ir: Implement bit reverse instruction.

2016-05-14 18:21:42 -07:00

IRJit.cpp

jit: Report blocks with uneaten VFPU prefixes.

2018-01-01 08:38:10 -08:00

IRJit.h

irjit: Speed up icache block invalidation.

2017-12-31 10:37:09 -08:00

IRPassSimplify.cpp

Attempts to counter crashes seen in the Google Play developer console

2016-12-01 22:07:03 +01:00

IRPassSimplify.h

jit-ir: Add load/store reorder and merge passes.

2016-05-17 21:24:13 -07:00

IRRegCache.cpp

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00

IRRegCache.h

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00