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522 Commits
Author SHA1 Message Date
Henrik RydgårdandGitHub 0ecfb6b112 Merge pull request #17992 from unknownbrackets/x86-jit-float 
x86jit: Implement trig instructions, couple other FPU
 2023-08-28 10:20:38 +02:00
Henrik RydgårdandGitHub 24e0cb013b Merge pull request #17991 from unknownbrackets/x86-jit-dot 
x86jit: Improve vdot performance
 2023-08-28 10:15:03 +02:00
Unknown W. Brackets f10444eb42 x86jit: Special case broadcast shuffles. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 61a99b4bac x86jit: Implement trig/reciprocals. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets 2e64abd2a0 x86jit: Improve some debug labels. 
Helps when running a profiler that reads these.
 2023-08-27 12:51:29 -07:00
Unknown W. Brackets 35fe15d718 x86jit: Do not use Vec4Dot for vdot.t. 
It was much slower to do so in LittleBigPlanet.
 2023-08-27 12:39:21 -07:00
Unknown W. Brackets 7d8dc0f8ab irjit: Detect clobber in lane change. 2023-08-27 12:27:05 -07:00
Unknown W. Brackets 6507251e83 irjit: Consider temps clobbered by block end. 2023-08-27 12:26:42 -07:00
Unknown W. Brackets f263698897 irjit: Cleanup temp purging on exit. 
We were sometimes considering it read by exit and not purging.
 2023-08-27 12:26:05 -07:00
Unknown W. Brackets d1a30334bf x86jit: Implement multiplies. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets 363f2b68e1 x86jit: Implement shifts. 2023-08-25 00:01:03 -07:00
Unknown W. Brackets 269a57a8b8 irjit: Fix vmin/vmax NAN handling. 
Oops, this needs to be signed.
 2023-08-23 06:50:42 -07:00
Henrik RydgårdandGitHub 77355a1568 Merge pull request #17954 from unknownbrackets/x86-jit-ir 
x86jit: Fix Ext8to32/Ext16to32, some reg issues
 2023-08-23 08:50:02 +02:00
Unknown W. Brackets efaf14a19f x86jit: Fix spilling zero register. 
We can't flush it, but it's likely not to get "clobbered".
 2023-08-22 23:29:13 -07:00
Unknown W. Brackets c397e2e4da x86jit: Flush reg if dirty on map as ptr. 2023-08-22 23:29:13 -07:00
Unknown W. Brackets 74e5e43fdc jit: Skip known prefix writes. 
If we already know what's in memory and it's default, we can skip
overwriting with default values.  This is common, actually.
 2023-08-22 23:26:31 -07:00
Unknown W. BracketsandHenrik Rydgård edcb156897 x86jit: Add Vec4 and Float load/store. 2023-08-22 10:39:46 +02:00
Unknown W. Brackets 07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets db34b85107 irjit: Allow flag-based allocation order. 
Sometimes backends have needs, like XMM0/v0-only, or similar.
 2023-08-21 20:46:05 -07:00
Unknown W. Brackets 5045cf012e x86jit: Fix flushing of zero register. 2023-08-20 22:28:54 -07:00
Unknown W. Brackets 81e24a9fee irjit: Fix regalloc clobber on exit. 2023-08-20 22:12:52 -07:00
Henrik RydgårdandGitHub 629d46ef5b Merge pull request #17938 from unknownbrackets/riscv-centralize 
Centralize IR regcache from RISC-V
 2023-08-20 23:47:02 +02:00
Henrik RydgårdandGitHub 6554b3eb75 Merge pull request #17939 from unknownbrackets/ir-vec-minor 
irjit: Implement vtfm 4x4 using dots
 2023-08-20 23:40:04 +02:00
Unknown W. Brackets 82fb41cba0 irjit: Implement vtfm 4x4 using dots. 2023-08-20 13:50:02 -07:00
Unknown W. Brackets 36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets 32d8f6196f irjit: Cut time flushing imm regs. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets 552cd88938 irjit: Skip some work in PurgeTemps. 2023-08-20 08:59:47 -07:00
Unknown W. Brackets 57123e8f9e irjit: Reserve some arrays that churn. 
Improves IR compile time by around 20-30%.
 2023-08-20 08:59:47 -07:00
Henrik RydgårdandGitHub cd1c5beb60 Merge pull request #17934 from unknownbrackets/riscv-centralize 
RISC-V: Centralize IR regcaches
 2023-08-20 14:49:18 +02:00
Unknown W. Brackets 161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
Unknown W. Brackets f3d4bd8c11 riscv: Centralize reg-as-pointer. 2023-08-19 21:24:36 -07:00
Unknown W. Brackets bd1d93ae6f irjit: Cleanup Write() calls with extra const. 
Some instructions, such as Vec4Blend, are encoded requiring the const
field, and this interface was designed when we used a pool.
 2023-08-19 16:23:42 -07:00
Unknown W. Brackets 92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets 4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
Unknown W. Brackets b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Henrik Rydgård 1b2cffe632 Address feedback 2023-08-14 11:06:20 +02:00
Henrik Rydgård ff6e118fff Get rid of a lot of ifdefs around presentation mode. Instead, set things dynamically. 2023-08-14 11:02:29 +02:00
Henrik RydgårdandGitHub 1beb01af6a Merge pull request #17905 from unknownbrackets/irjit-opt 
irjit: Implement some missing, handle partial Vec4s more
 2023-08-14 07:49:45 +02:00
Unknown W. Brackets 3f8f8d36d9 riscv: Fix crash on clear icache. 
Oops, can't avoid marking all blocks invalid.  Luckily a syscall should
always take more bytes than the bail invalidated block code.
 2023-08-13 18:25:46 -07:00
Unknown W. Brackets 159b41a0fa irjit: Fuse unaligned svl.q/svr.q together. 
They're almost never used outside paired, which we can do on most
platforms easily.
 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 5729de90d2 irjit: Use more partial Vec4s / Vec4Blend. 2023-08-13 18:10:40 -07:00
Unknown W. Brackets 2e6dbab5fa irjit: Add flag to prefer Vec4, use for add/sub. 
This will improve things when using SIMD.
 2023-08-13 18:10:40 -07:00