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Merge pull request #17944 from hrydgard/some-ir-alu

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Implement a few ALU ops in the x86 JIT-IR backend.
This commit is contained in:
Henrik Rydgård authored and GitHub committed 2023-08-22 16:38:28 +02:00
2 parents 11c40e6889 6a3840d9b6
commit a5a2af4892
2 files changed
+58 -7
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Core/MIPS/x86/X64IRCompALU.cpp
+55 -4
View File
@@ -110,7 +110,11 @@ void X64JitBackend::CompIR_Arith(IRInst inst) {
break;
case IROp::Neg:
CompIR_Generic(inst);
regs_.Map(inst);
if (inst.dest != inst.src1) {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
}
NEG(32, regs_.R(inst.dest));
break;
default:
@@ -131,8 +135,19 @@ void X64JitBackend::CompIR_Assign(IRInst inst) {
break;
case IROp::Ext8to32:
#if PPSSPP_ARCH(X86)
DISABLE; // 8-bit registers need special handling
#endif
regs_.Map(inst);
MOVZX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
break;
case IROp::Ext16to32:
CompIR_Generic(inst);
#if PPSSPP_ARCH(X86)
DISABLE; // 8-bit registers need special handling
#endif
regs_.Map(inst);
MOVZX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
break;
default:
@@ -145,9 +160,16 @@ void X64JitBackend::CompIR_Bits(IRInst inst) {
CONDITIONAL_DISABLE;
switch (inst.op) {
case IROp::BSwap32:
regs_.Map(inst);
if (inst.src1 != inst.dest) {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
}
BSWAP(32, regs_.RX(inst.dest));
break;
case IROp::ReverseBits:
case IROp::BSwap16:
case IROp::BSwap32:
case IROp::Clz:
CompIR_Generic(inst);
break;
@@ -229,9 +251,38 @@ void X64JitBackend::CompIR_Logic(IRInst inst) {
switch (inst.op) {
case IROp::And:
regs_.Map(inst);
if (inst.dest == inst.src1) {
AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
AND(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break;
case IROp::Or:
regs_.Map(inst);
if (inst.dest == inst.src1) {
OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
OR(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break;
case IROp::Xor:
CompIR_Generic(inst);
regs_.Map(inst);
if (inst.dest == inst.src1) {
XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
} else if (inst.dest == inst.src2) {
XOR(32, regs_.R(inst.dest), regs_.R(inst.src1));
} else {
MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
}
break;
case IROp::AndConst:
Core/MIPS/x86/X64IRRegCache.cpp
+3 -3
View File
@@ -191,9 +191,9 @@ X64Reg X64IRRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {
}
X64Reg X64IRRegCache::MapVec4(IRReg first, MIPSMap mapFlags) {
_dbg_assert_(IsValidFPR(mipsReg));
_dbg_assert_((mipsReg & 3) == 0);
_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
_dbg_assert_(IsValidFPR(first));
_dbg_assert_((first & 3) == 0);
_dbg_assert_(mr[first + 32].loc == MIPSLoc::MEM || mr[first + 32].loc == MIPSLoc::FREG);
IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, first + 32, 4, mapFlags);
if (nreg != -1)