From b67741509c6d0886b3c927a98fe3f5629794bad6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Mon, 21 Aug 2023 14:32:41 +0200
Subject: [PATCH 1/4] Implement a few ALU ops in the x86 JIT-from-IR.

---
 Core/MIPS/x86/X64IRCompALU.cpp | 44 +++++++++++++++++++++++++++++++---
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp
index daee4db18b..d37de92d28 100644
--- a/Core/MIPS/x86/X64IRCompALU.cpp
+++ b/Core/MIPS/x86/X64IRCompALU.cpp
@@ -110,7 +110,11 @@ void X64JitBackend::CompIR_Arith(IRInst inst) {
 		break;
 
 	case IROp::Neg:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		if (inst.dest != inst.src1) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		}
+		NEG(32, regs_.R(inst.dest));
 		break;
 
 	default:
@@ -131,8 +135,13 @@ void X64JitBackend::CompIR_Assign(IRInst inst) {
 		break;
 
 	case IROp::Ext8to32:
+		regs_.Map(inst);
+		MOVZX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
+		break;
+
 	case IROp::Ext16to32:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		MOVZX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
 		break;
 
 	default:
@@ -229,9 +238,38 @@ void X64JitBackend::CompIR_Logic(IRInst inst) {
 
 	switch (inst.op) {
 	case IROp::And:
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
+		break;
 	case IROp::Or:
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
+		break;
+
 	case IROp::Xor:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
 		break;
 
 	case IROp::AndConst:

From c5a076487e5dec6f29575fb53155a5af63f9c03c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Tue, 22 Aug 2023 16:09:45 +0200
Subject: [PATCH 2/4] Disable extends on x86-32

---
 Core/MIPS/x86/X64IRCompALU.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp
index d37de92d28..0008edc039 100644
--- a/Core/MIPS/x86/X64IRCompALU.cpp
+++ b/Core/MIPS/x86/X64IRCompALU.cpp
@@ -135,11 +135,17 @@ void X64JitBackend::CompIR_Assign(IRInst inst) {
 		break;
 
 	case IROp::Ext8to32:
+#if PPSSPP_ARCH(X86)
+		DISABLE;  // 8-bit registers need special handling
+#endif
 		regs_.Map(inst);
 		MOVZX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
 		break;
 
 	case IROp::Ext16to32:
+#if PPSSPP_ARCH(X86)
+		DISABLE;  // 8-bit registers need special handling
+#endif
 		regs_.Map(inst);
 		MOVZX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
 		break;

From 7384d3d49f7e9b03cd1b6c8cc43d2ff761f0c977 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Tue, 22 Aug 2023 16:15:07 +0200
Subject: [PATCH 3/4] Debug mode buildfix

---
 Core/MIPS/x86/X64IRRegCache.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Core/MIPS/x86/X64IRRegCache.cpp b/Core/MIPS/x86/X64IRRegCache.cpp
index 07c1be33a3..e6f053a276 100644
--- a/Core/MIPS/x86/X64IRRegCache.cpp
+++ b/Core/MIPS/x86/X64IRRegCache.cpp
@@ -191,9 +191,9 @@ X64Reg X64IRRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {
 }
 
 X64Reg X64IRRegCache::MapVec4(IRReg first, MIPSMap mapFlags) {
-	_dbg_assert_(IsValidFPR(mipsReg));
-	_dbg_assert_((mipsReg & 3) == 0);
-	_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
+	_dbg_assert_(IsValidFPR(first));
+	_dbg_assert_((first & 3) == 0);
+	_dbg_assert_(mr[first + 32].loc == MIPSLoc::MEM || mr[first + 32].loc == MIPSLoc::FREG);
 
 	IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, first + 32, 4, mapFlags);
 	if (nreg != -1)

From 6a3840d9b6a85d94e7a71c94b650389afcbaae52 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= <hrydgard@gmail.com>
Date: Tue, 22 Aug 2023 16:18:03 +0200
Subject: [PATCH 4/4] Implement bswap just because

---
 Core/MIPS/x86/X64IRCompALU.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp
index 0008edc039..505c0b6f2a 100644
--- a/Core/MIPS/x86/X64IRCompALU.cpp
+++ b/Core/MIPS/x86/X64IRCompALU.cpp
@@ -160,9 +160,16 @@ void X64JitBackend::CompIR_Bits(IRInst inst) {
 	CONDITIONAL_DISABLE;
 
 	switch (inst.op) {
+	case IROp::BSwap32:
+		regs_.Map(inst);
+		if (inst.src1 != inst.dest) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		}
+		BSWAP(32, regs_.RX(inst.dest));
+		break;
+
 	case IROp::ReverseBits:
 	case IROp::BSwap16:
-	case IROp::BSwap32:
 	case IROp::Clz:
 		CompIR_Generic(inst);
 		break;