diff --git a/Core/MIPS/x86/X64IRCompALU.cpp b/Core/MIPS/x86/X64IRCompALU.cpp
index daee4db18b..505c0b6f2a 100644
--- a/Core/MIPS/x86/X64IRCompALU.cpp
+++ b/Core/MIPS/x86/X64IRCompALU.cpp
@@ -110,7 +110,11 @@ void X64JitBackend::CompIR_Arith(IRInst inst) {
 		break;
 
 	case IROp::Neg:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		if (inst.dest != inst.src1) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		}
+		NEG(32, regs_.R(inst.dest));
 		break;
 
 	default:
@@ -131,8 +135,19 @@ void X64JitBackend::CompIR_Assign(IRInst inst) {
 		break;
 
 	case IROp::Ext8to32:
+#if PPSSPP_ARCH(X86)
+		DISABLE;  // 8-bit registers need special handling
+#endif
+		regs_.Map(inst);
+		MOVZX(32, 8, regs_.RX(inst.dest), regs_.R(inst.src1));
+		break;
+
 	case IROp::Ext16to32:
-		CompIR_Generic(inst);
+#if PPSSPP_ARCH(X86)
+		DISABLE;  // 8-bit registers need special handling
+#endif
+		regs_.Map(inst);
+		MOVZX(32, 16, regs_.RX(inst.dest), regs_.R(inst.src1));
 		break;
 
 	default:
@@ -145,9 +160,16 @@ void X64JitBackend::CompIR_Bits(IRInst inst) {
 	CONDITIONAL_DISABLE;
 
 	switch (inst.op) {
+	case IROp::BSwap32:
+		regs_.Map(inst);
+		if (inst.src1 != inst.dest) {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		}
+		BSWAP(32, regs_.RX(inst.dest));
+		break;
+
 	case IROp::ReverseBits:
 	case IROp::BSwap16:
-	case IROp::BSwap32:
 	case IROp::Clz:
 		CompIR_Generic(inst);
 		break;
@@ -229,9 +251,38 @@ void X64JitBackend::CompIR_Logic(IRInst inst) {
 
 	switch (inst.op) {
 	case IROp::And:
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			AND(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
+		break;
 	case IROp::Or:
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			OR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
+		break;
+
 	case IROp::Xor:
-		CompIR_Generic(inst);
+		regs_.Map(inst);
+		if (inst.dest == inst.src1) {
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		} else if (inst.dest == inst.src2) {
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src1));
+		} else {
+			MOV(32, regs_.R(inst.dest), regs_.R(inst.src1));
+			XOR(32, regs_.R(inst.dest), regs_.R(inst.src2));
+		}
 		break;
 
 	case IROp::AndConst:
diff --git a/Core/MIPS/x86/X64IRRegCache.cpp b/Core/MIPS/x86/X64IRRegCache.cpp
index 07c1be33a3..e6f053a276 100644
--- a/Core/MIPS/x86/X64IRRegCache.cpp
+++ b/Core/MIPS/x86/X64IRRegCache.cpp
@@ -191,9 +191,9 @@ X64Reg X64IRRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {
 }
 
 X64Reg X64IRRegCache::MapVec4(IRReg first, MIPSMap mapFlags) {
-	_dbg_assert_(IsValidFPR(mipsReg));
-	_dbg_assert_((mipsReg & 3) == 0);
-	_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
+	_dbg_assert_(IsValidFPR(first));
+	_dbg_assert_((first & 3) == 0);
+	_dbg_assert_(mr[first + 32].loc == MIPSLoc::MEM || mr[first + 32].loc == MIPSLoc::FREG);
 
 	IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, first + 32, 4, mapFlags);
 	if (nreg != -1)