ppsspp

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Henrik RydgårdandClaude Fable 5.1 960514d63a arm64 JIT: Gate the VFPU ops with odd prefix rules the way the IR does

The arm64 JIT applied the plain prefix rules to every op. Several ops
don't follow them, and the interpreter and IR frontend know which:

- vabs and vneg are vmov with the abs/negate bit forced, so a negate in
  the S prefix doesn't negate twice.
- vsat1 doesn't apply the D saturation.
- vrcp, vrsq, vsqrt, vnrcp (and the rest of that group) apply S and D to
  the last lane only, from prefix position 0.
- vzero, vone and vidt are changed by a pending S prefix.
- vdiv, vscl, vfad/vavg and vrot each have their own rule.
- vuc2i and friends with an S prefix.

Hand these to the interpreter, exactly where the IR frontend does. Also
mask what mtvc writes to a control register (the low 20 bits of a prefix,
12 of the D prefix), as the IR already did.

Goes from 19 ops differing from hardware in cpu/vfpu/prefix_consume to
the 3 that differ on every core, and clears cpu/vfpu/prefix_ctrl.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

2026-09-22 11:37:48 -06:00

Arm64Asm.cpp

Add a utility function for all the ABIs to call functions with a pointer arg. Use to call Advance from the JIT with the MIPSContext. Indent some code better.

2026-08-13 08:09:30 +02:00

Arm64CompALU.cpp

Code cleanup. Don't use gpr.SetRegImm where all we do is write to a scratch register

2026-02-10 19:28:53 +01:00

Arm64CompBranch.cpp

Plumb through the PC value for syscalls, so we can get better diagnostics for unresolved ones.

2026-08-15 19:14:13 +02:00

Arm64CompFPU.cpp

Implement MMIO for the JIT (by falling back to the interpreter for load/stores from kernel addresses)