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Henrik RydgårdandClaude Fable 5.1
960514d63a
The arm64 JIT applied the plain prefix rules to every op. Several ops don't follow them, and the interpreter and IR frontend know which: - vabs and vneg are vmov with the abs/negate bit forced, so a negate in the S prefix doesn't negate twice. - vsat1 doesn't apply the D saturation. - vrcp, vrsq, vsqrt, vnrcp (and the rest of that group) apply S and D to the last lane only, from prefix position 0. - vzero, vone and vidt are changed by a pending S prefix. - vdiv, vscl, vfad/vavg and vrot each have their own rule. - vuc2i and friends with an S prefix. Hand these to the interpreter, exactly where the IR frontend does. Also mask what mtvc writes to a control register (the low 20 bits of a prefix, 12 of the D prefix), as the IR already did. Goes from 19 ops differing from hardware in cpu/vfpu/prefix_consume to the 3 that differ on every core, and clears cpu/vfpu/prefix_ctrl. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>