Henrik RydgårdandClaude Opus 5.5 b175bc859a IR JIT: Grow the native code space to 24 MB ...

Big games fill 16 MB in normal play. It's now one constant shared by
every backend. ARM32's 32 MB branch range is the limit on going higher
there.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-10-17 15:11:47 +02:00

..

RiscVAsm.cpp

RISC-V and LoongArch64 IR JITs: Name the fixed code routines, and profile on Linux

2026-10-15 15:17:50 +02:00

RiscVCompALU.cpp

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVCompBranch.cpp

RISC-V and LoongArch64 IR JITs: Look up the block for a jump to a register at the jump

2026-10-15 15:17:37 +02:00

RiscVCompFPU.cpp

VFPU: vmin and vmax order zeros and denormals as equal, on every core

2026-10-14 11:59:35 +02:00

RiscVCompLoadStore.cpp

IR native backends: Fix ll into $zero, and sc losing its result

2026-10-14 00:10:00 +02:00

RiscVCompSystem.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVCompVec.cpp

RISC-V and LoongArch64 IR JITs: Vec4 vmin, vmax, vslt, vsge and vi2f

2026-10-15 15:17:50 +02:00

RiscVJit.cpp

IR JIT: Grow the native code space to 24 MB

2026-10-17 15:11:47 +02:00

RiscVJit.h

RISC-V and LoongArch64 IR JITs: Name the fixed code routines, and profile on Linux

2026-10-15 15:17:50 +02:00

RiscVRegCache.cpp

RISC-V IR JIT: Run Vec4VfpuDot through a shared routine

2026-10-15 14:42:00 +02:00

RiscVRegCache.h

RISC-V IR JIT: Run Vec4VfpuDot through a shared routine

2026-10-15 14:42:00 +02:00

RiscVVfpuDot.h

RISC-V IR JIT: Run Vec4VfpuDot through a shared routine

2026-10-15 14:42:00 +02:00