mirror of
https://github.com/hrydgard/ppsspp.git
synced 2026-10-20 09:49:03 +02:00
Henrik RydgårdandClaude Opus 5.5
c6c9e8ff85
The accurate dot products went to the IR interpreter, flushing everything around each one. Now the JIT stores the operands to mips->vfpuDotArgs and calls a routine generated at startup, which clobbers only registers late in the allocation order. Inf and NaN go to vfpu_dot_reference(). The routine is vfpu_dot_scalar() in RV64, using Zbb and Zicond where it has them, or with the V extension, vfpu_dot_sse2() in RVV. The rounding at the end comes from FCVT.S.LU with a static round-to-nearest-even, which also gives the exponent, so there's no need for Zbb's CLZ. VFPUDotJit runs each variant the host can run against the reference on VFPUDot's inputs, the RVV one with poisoned vector registers. PPSSPP_CPUFUZZ_HOSTEXT=- now turns V off too. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
98 lines
3.6 KiB
C++
98 lines
3.6 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include <initializer_list>
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#include "Common/RiscVEmitter.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/IR/IRJit.h"
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#include "Core/MIPS/IR/IRRegCache.h"
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namespace RiscVJitConstants {
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// Note: we don't support 32-bit or 128-bit CPUs currently.
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constexpr int XLEN = 64;
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const RiscVGen::RiscVReg DOWNCOUNTREG = RiscVGen::X24;
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const RiscVGen::RiscVReg JITBASEREG = RiscVGen::X25;
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const RiscVGen::RiscVReg CTXREG = RiscVGen::X26;
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const RiscVGen::RiscVReg MEMBASEREG = RiscVGen::X27;
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// TODO: Experiment. X7-X13 are compressed regs. X8/X9 are saved so nice for static alloc, though.
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const RiscVGen::RiscVReg SCRATCH1 = RiscVGen::X10;
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const RiscVGen::RiscVReg SCRATCH2 = RiscVGen::X11;
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} // namespace RiscVJitConstants
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class RiscVRegCache : public IRNativeRegCacheBase {
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public:
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RiscVRegCache(MIPSComp::JitOptions *jo);
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void Init(RiscVGen::RiscVEmitter *emitter);
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// May fail and return INVALID_REG if it needs flushing.
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RiscVGen::RiscVReg TryMapTempImm(IRReg reg);
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// Returns an RV register containing the requested MIPS register.
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RiscVGen::RiscVReg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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RiscVGen::RiscVReg MapGPRAsPointer(IRReg reg);
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RiscVGen::RiscVReg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT);
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RiscVGen::RiscVReg MapWithFPRTemp(const IRInst &inst);
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bool IsNormalized32(IRReg reg);
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// Copies to another reg if specified, otherwise same reg.
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RiscVGen::RiscVReg Normalize32(IRReg reg, RiscVGen::RiscVReg destReg = RiscVGen::INVALID_REG);
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void FlushBeforeCall();
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// Flushes whatever guest state these registers hold, for code that clobbers them.
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void FlushHostRegs(std::initializer_list<RiscVGen::RiscVReg> regs);
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RiscVGen::RiscVReg GetAndLockTempGPR();
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RiscVGen::RiscVReg R(IRReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer
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RiscVGen::RiscVReg RPtr(IRReg preg); // Returns a cached register, if it has been mapped as a pointer
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RiscVGen::RiscVReg F(IRReg preg);
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// These are called once on startup to generate functions, that you should then call.
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void EmitLoadStaticRegisters();
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void EmitSaveStaticRegisters();
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protected:
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void SetupInitialRegs() override;
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const StaticAllocation *GetStaticAllocations(int &count) const override;
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const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override;
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void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override;
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bool IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) override;
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void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override;
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void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override;
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void StoreRegValue(IRReg mreg, uint32_t imm) override;
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private:
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RiscVGen::RiscVEmitter *emit_ = nullptr;
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enum {
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NUM_RVGPR = 32,
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NUM_RVFPR = 32,
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NUM_RVVPR = 32,
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};
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};
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