mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
59b6b4de78
Like the ARM64 JIT (e33f38afa6), each jr and jalr does the dispatcher's
lookup itself, for an indirect branch of its own, and goes to the
dispatcher when out of downcount or with no block yet.
A bad target now faults in the block rather than at dispatchFetch, so the
fault handler takes any fault in the block shadow as a bad jump, with the
masked target from the address. That covers ARM64's too, which was handled
as a bad memory access.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
161 lines
4.0 KiB
C++
161 lines
4.0 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "Core/MIPS/RiscV/RiscVJit.h"
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#include "Core/MIPS/RiscV/RiscVRegCache.h"
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// This file contains compilation for exits.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace RiscVGen;
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using namespace RiscVJitConstants;
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void RiscVJitBackend::CompIR_Exit(IRInst inst) {
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CONDITIONAL_DISABLE;
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RiscVReg exitReg = INVALID_REG;
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switch (inst.op) {
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case IROp::ExitToConst:
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FlushAll();
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WriteConstExit(inst.constant);
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break;
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case IROp::ExitToReg:
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exitReg = regs_.MapGPR(inst.src1);
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FlushAll();
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MV(SCRATCH1, exitReg);
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// The dispatcher's lookup, here: each of these then has its own indirect branch, which the
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// CPU predicts far better than one shared by every jr. Anything unusual goes the long way.
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MovToPC(SCRATCH1);
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{
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// Out of the downcount, or no block yet: the dispatcher, with the PC stored.
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FixupBranch inTime = BGE(DOWNCOUNTREG, R_ZERO);
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QuickJ(R_RA, hooks_.dispatcher);
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SetJumpTarget(inTime);
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LI(SCRATCH2, (u32)Memory::BLOCK_SHADOW_ENTRY_MASK);
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AND(SCRATCH1, SCRATCH1, SCRATCH2);
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LI(SCRATCH2, Memory::blockShadow, X7);
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ADD(SCRATCH1, SCRATCH1, SCRATCH2);
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LWU(SCRATCH1, SCRATCH1, 0);
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FixupBranch found = BNE(SCRATCH1, R_ZERO);
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QuickJ(R_RA, dispatcherNoCheck_);
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SetJumpTarget(found);
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ADD(SCRATCH1, JITBASEREG, SCRATCH1);
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JR(SCRATCH1);
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}
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break;
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case IROp::ExitToPC:
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FlushAll();
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QuickJ(R_RA, dispatcherCheckCoreState_);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void RiscVJitBackend::CompIR_ExitIf(IRInst inst) {
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CONDITIONAL_DISABLE;
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RiscVReg lhs = INVALID_REG;
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RiscVReg rhs = INVALID_REG;
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FixupBranch fixup;
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switch (inst.op) {
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case IROp::ExitToConstIfEq:
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case IROp::ExitToConstIfNeq:
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regs_.Map(inst);
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// We can't use SCRATCH1, which is destroyed by FlushAll()... but cheat and use R_RA.
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NormalizeSrc12(inst, &lhs, &rhs, R_RA, SCRATCH2, true);
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FlushAll();
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switch (inst.op) {
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case IROp::ExitToConstIfEq:
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fixup = BNE(lhs, rhs);
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break;
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case IROp::ExitToConstIfNeq:
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fixup = BEQ(lhs, rhs);
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break;
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default:
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INVALIDOP;
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break;
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}
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WriteConstExit(inst.constant);
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SetJumpTarget(fixup);
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break;
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case IROp::ExitToConstIfGtZ:
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case IROp::ExitToConstIfGeZ:
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case IROp::ExitToConstIfLtZ:
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case IROp::ExitToConstIfLeZ:
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regs_.Map(inst);
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NormalizeSrc1(inst, &lhs, SCRATCH2, true);
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FlushAll();
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switch (inst.op) {
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case IROp::ExitToConstIfGtZ:
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fixup = BGE(R_ZERO, lhs);
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break;
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case IROp::ExitToConstIfGeZ:
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fixup = BLT(lhs, R_ZERO);
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break;
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case IROp::ExitToConstIfLtZ:
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fixup = BGE(lhs, R_ZERO);
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break;
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case IROp::ExitToConstIfLeZ:
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fixup = BLT(R_ZERO, lhs);
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break;
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default:
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INVALIDOP;
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break;
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}
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WriteConstExit(inst.constant);
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SetJumpTarget(fixup);
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break;
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case IROp::ExitToConstIfFpTrue:
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case IROp::ExitToConstIfFpFalse:
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// Note: not used.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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