15 Commits

Include renames

Author	SHA1	Message	Date
Unknown W. Brackets	e34736fbb2	riscv: Reduce norms in Slt/Sltu overlap cases. ... We can skip an SEXT.W in common cases where the dest and src overlap.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	d1dc346899	riscv: Fix pointer add/sub.	2023-07-30 14:19:28 -07:00
Unknown W. Brackets	70ff18a463	riscv: Implement count leading zeros.	2023-07-30 00:02:10 -07:00
Unknown W. Brackets	e2765db4dc	riscv: Implement division.	2023-07-29 19:02:15 -07:00
Unknown W. Brackets	18c48681a8	riscv: Implement multiply instructions.	2023-07-23 18:01:50 -07:00
Unknown W. Brackets	7f4689e8fa	riscv: Use direct SLI/SLIU instructions. ... Derp, I forgot these existed on RISC-V for a moment.	2023-07-23 18:01:46 -07:00
Unknown W. Brackets	f7f7531500	riscv: Fix min/max normalization.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	92694e765f	riscv: Implement conditional moves.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	2c7da94bd1	riscv: Implement shifts and compares.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	5ed2f0d559	riscv: Implement logic ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	d31eded9ba	riscv: Allow dirty pointers, explicitly.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	05a2789cf4	riscv: Implement some simple assign instructions.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00