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Author SHA1 Message Date
Henrik Rydgård 042dcc170f Merge pull request #8735 from hrydgard/ir-jit-test 
Buildfixes + Travis caching
 2016-05-14 11:17:55 +02:00
Unknown W. Brackets e2aca38f8b Try enabling Travis caching. 2016-05-14 02:13:17 -07:00
Unknown W. Brackets efc8a8e353 Hack to make Symbian build. 2016-05-13 23:56:17 -07:00
Unknown W. Brackets b7224e269c Qt: Remove CPU core option from menu. 
We've removed on Windows too, and this fixes a build error.
 2016-05-13 23:56:16 -07:00
Henrik Rydgard b7091a8f5d Simplifications and fixes 2016-05-13 21:02:23 +02:00
Henrik Rydgard 5923013d65 Simple workaround for timing issue with coreState after syscall. 
Also fixes off by one in ForceCheck.
 2016-05-13 20:21:19 +02:00
Henrik Rydgard 5b2504120d Optimize some common prefixes 2016-05-13 20:15:20 +02:00
Henrik Rydgard 91a6cf5e44 Add a couple more passes (2-op, optimize f<->v fp moves) 2016-05-13 20:14:03 +02:00
Henrik Rydgard f636b2a315 Minor build and other fixes 2016-05-13 19:31:27 +02:00
Henrik Rydgård fc9159fbda Merge pull request #8733 from unknownbrackets/ir-jit 
jit-ir: Optimize out beql; break; sequences
 2016-05-13 17:06:23 +02:00
Unknown W. Brackets 066b0b7fdf jit-ir: Optimize out beql; break; sequences. 
These are often used following divs, and are harmless.  Things get a bit
easier if we just never compile them.
 2016-05-13 07:59:39 -07:00
Henrik Rydgård 49b133971c Merge pull request #8732 from unknownbrackets/ir-jit 
Add a pass to remove temporary regs
 2016-05-13 10:11:13 +02:00
Unknown W. Brackets 7b43e0e59d jit-ir: Add nan/inf compares. 
Without this, Gods Eater Burst crashes before going in game.
 2016-05-12 22:53:21 -07:00
Unknown W. Brackets 9e3572dc63 jit-ir: Improve vidt to handle more cases. 2016-05-12 22:40:26 -07:00
Unknown W. Brackets f52120353b jit-ir: Apply prefixes for vector init ops. 
Without this, Gods Eater Burst is horribly broken.
 2016-05-12 22:29:31 -07:00
Unknown W. Brackets c11c0465de jir-ir: Correct vftm SIMD regs. 2016-05-12 21:29:58 -07:00
Unknown W. Brackets 1ddb2fbfb9 jit-ir: Fix non-SSE Vec4Scale. 2016-05-12 21:02:56 -07:00
Unknown W. Brackets 57b3dbff7e jit-ir: Avoid flushing on a few Vec4 ops. 2016-05-12 21:01:46 -07:00
Unknown W. Brackets a8126ca132 jit-ir: Add some missing CONDITIONAL_DISABLEs. 2016-05-12 20:56:47 -07:00
Unknown W. Brackets 29ed8d2201 jit-ir: ExitToReg doesn't write to registers. 2016-05-12 18:34:27 -07:00
Unknown W. Brackets 9f183c97ba jit-ir: Prevent reading ahead for each reg write. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets d06c6c080c jit-ir: Expand unused regs to regular GPRs. 2016-05-12 18:30:55 -07:00
Unknown W. Brackets 99468c6fc1 jit-ir: Optimize out unused temp regs. 
This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
 2016-05-12 18:30:53 -07:00
Henrik Rydgard 7268abec61 IR: vcmp, vcmov, vhdp 2016-05-12 22:35:31 +02:00
Henrik Rydgard 1851458628 Bugfixes 2016-05-12 20:28:59 +02:00
Henrik Rydgard c69a8c07dc Forgot this 2016-05-12 20:20:59 +02:00
Henrik Rydgard 850d0abc91 IR: More VFPU. Support normal fp compares. 2016-05-12 20:16:15 +02:00
Henrik Rydgard 182674cddf IR: SIMD another matrix orientation. Fix various issues. 2016-05-12 13:10:26 +02:00
Henrik Rydgard cb251ea93f Crashfix in savestate (hmmmm...) 2016-05-12 12:18:12 +02:00
Henrik Rydgard 2cbfb192c4 IR: Lots more VFPU support, some with SIMD 2016-05-12 12:17:25 +02:00
Henrik Rydgard 219548b8e2 Prefix prep 2016-05-11 00:16:07 +02:00
Henrik Rydgard b3dd36982f Prefix prep 2016-05-10 23:14:26 +02:00
Henrik Rydgard db1d1ff9fd IR: Merge the FPU and VFPU instruction sets, no reason to keep them apart 2016-05-10 22:55:27 +02:00
Henrik Rydgard 45efcda6b1 IR: Some more VFPU 2016-05-10 21:50:08 +02:00
Henrik Rydgard 558bb197c7 More VFPU 2016-05-09 23:47:56 +02:00
Henrik Rydgard a5d5c5ce2b Do the voffset remapping before the IR. This will let us easily add some virtual VFPU registers for the IR to the end, plus it's slightly faster. 2016-05-09 22:40:59 +02:00
Henrik Rydgard 28087a6088 IRFrontend shouldn't know about IRBlock 2016-05-09 20:18:22 +02:00
Henrik Rydgard e711a47a75 Complete the separation of the IR compiler frontend from the "Jit" 2016-05-09 20:05:06 +02:00
Henrik Rydgard e806c369b2 Separate the IR frontend from the IR "Jit" 2016-05-09 19:57:18 +02:00
Henrik Rydgard 6e44e97ffa Refactor prep: Split JitInterface into MIPSFrontendInterface and JitInterface 2016-05-09 19:41:39 +02:00
Henrik Rydgard f50617d679 Skip const flush on set float constant 2016-05-09 18:47:53 +02:00
Henrik Rydgård b1a180d9fb Merge pull request #8731 from unknownbrackets/ir-jit 
jit-ir: Correct downcount handling
 2016-05-09 10:42:26 +02:00
Unknown W. Brackets eb6551d72a jit-ir: Correct downcount handling. 
Oops, was wrong - already accounted for delay slots.  Clear so we don't
double count when emitting a syscall.

Fixes FF4 utility msg flickering.
 2016-05-09 01:13:53 -07:00
Henrik Rydgård dee2a7e651 Merge pull request #8727 from unknownbrackets/ir-jit 
Apply more constant propagation to IR
 2016-05-09 10:05:53 +02:00
Unknown W. Brackets ccb8f8d77e jit-ir: Fix replacement hooks. 2016-05-09 00:36:38 -07:00
Unknown W. Brackets f6d245f3c4 jit-ir: Remove redundant simplify pass. 
This is just doing the same thing as the const folding pass, really.
 2016-05-09 00:13:01 -07:00
Unknown W. Brackets f638477b9a jit-ir: Add the rest to PropagateConstants. 
Just for completeness.
 2016-05-08 22:17:39 -07:00
Unknown W. Brackets 7ce923d01f jit-ir: Fix SetConstV. 
Oops.
 2016-05-08 22:11:53 -07:00
Unknown W. Brackets 6bd31ecb27 jit-ir: Flush consts better for a few f/v ops. 2016-05-08 21:37:46 -07:00
Unknown W. Brackets 5221a02db4 jit-ir: Propagate constants for shifts. 
This might optimize away an IRTEMP_0 in such cases.
 2016-05-08 19:11:58 -07:00