preserve-emulation/ppsspp
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Do the voffset remapping before the IR. This will let us easily add some virtual VFPU registers for the IR to the end, plus it's slightly faster.

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Henrik Rydgard committed 2016-05-09 22:40:59 +02:00
1 parent 28087a6088
commit a5d5c5ce2b
3 files changed
+15 -16
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Core/MIPS/IR/IRCompVFPU.cpp
+10 -10
View File
@@ -192,20 +192,20 @@ namespace MIPSComp {
case 54: //lv.q
{
// TODO: Add vector load/store instruction to the IR
ir.Write(IROp::LoadFloatV, vregs[0], rs, ir.AddConstant(imm));
ir.Write(IROp::LoadFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
ir.Write(IROp::LoadFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
ir.Write(IROp::LoadFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
ir.Write(IROp::LoadFloatV, voffset[vregs[0]], rs, ir.AddConstant(imm));
ir.Write(IROp::LoadFloatV, voffset[vregs[1]], rs, ir.AddConstant(imm + 4));
ir.Write(IROp::LoadFloatV, voffset[vregs[2]], rs, ir.AddConstant(imm + 8));
ir.Write(IROp::LoadFloatV, voffset[vregs[3]], rs, ir.AddConstant(imm + 12));
}
break;
case 62: //sv.q
{
// CC might be set by slow path below, so load regs first.
ir.Write(IROp::StoreFloatV, vregs[0], rs, ir.AddConstant(imm));
ir.Write(IROp::StoreFloatV, vregs[1], rs, ir.AddConstant(imm + 4));
ir.Write(IROp::StoreFloatV, vregs[2], rs, ir.AddConstant(imm + 8));
ir.Write(IROp::StoreFloatV, vregs[3], rs, ir.AddConstant(imm + 12));
ir.Write(IROp::StoreFloatV, voffset[vregs[0]], rs, ir.AddConstant(imm));
ir.Write(IROp::StoreFloatV, voffset[vregs[1]], rs, ir.AddConstant(imm + 4));
ir.Write(IROp::StoreFloatV, voffset[vregs[2]], rs, ir.AddConstant(imm + 8));
ir.Write(IROp::StoreFloatV, voffset[vregs[3]], rs, ir.AddConstant(imm + 12));
}
break;
@@ -274,7 +274,7 @@ namespace MIPSComp {
// rt = 0, imm = 255 appears to be used as a CPU interlock by some games.
if (rt != 0) {
if (imm < 128) { //R(rt) = VI(imm);
ir.Write(IROp::VMovToGPR, rt, imm);
ir.Write(IROp::VMovToGPR, rt, voffset[imm]);
} else {
DISABLE;
}
@@ -283,7 +283,7 @@ namespace MIPSComp {
case 7: // mtv
if (imm < 128) {
ir.Write(IROp::VMovFromGPR, imm, rt);
ir.Write(IROp::VMovFromGPR, voffset[imm], rt);
} else {
DISABLE;
}
Core/MIPS/IR/IRFrontend.cpp
-1
View File
@@ -26,7 +26,6 @@
#include "Core/MIPS/IR/IRFrontend.h"
#include "Core/MIPS/IR/IRRegCache.h"
#include "Core/MIPS/IR/IRJit.h"
#include "Core/MIPS/IR/IRPassSimplify.h"
#include "Core/MIPS/IR/IRInterpreter.h"
Core/MIPS/IR/IRInterpreter.cpp
+5 -5
View File
@@ -21,7 +21,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
memcpy(&mips->f[inst->dest], &constPool[inst->src1], 4);
break;
case IROp::SetConstV:
memcpy(&mips->v[voffset[inst->dest]], &constPool[inst->src1], 4);
memcpy(&mips->v[inst->dest], &constPool[inst->src1], 4);
break;
case IROp::Add:
mips->r[inst->dest] = mips->r[inst->src1] + mips->r[inst->src2];
@@ -88,7 +88,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
mips->f[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
break;
case IROp::LoadFloatV:
mips->v[voffset[inst->dest]] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
mips->v[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
break;
case IROp::Store8:
@@ -104,7 +104,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
Memory::WriteUnchecked_Float(mips->f[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
break;
case IROp::StoreFloatV:
Memory::WriteUnchecked_Float(mips->v[voffset[inst->src3]], mips->r[inst->src1] + constPool[inst->src2]);
Memory::WriteUnchecked_Float(mips->v[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
break;
case IROp::ShlImm:
@@ -314,10 +314,10 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
break;
case IROp::VMovFromGPR:
memcpy(&mips->v[voffset[inst->dest]], &mips->r[inst->src1], 4);
memcpy(&mips->v[inst->dest], &mips->r[inst->src1], 4);
break;
case IROp::VMovToGPR:
memcpy(&mips->r[inst->dest], &mips->v[voffset[inst->src1]], 4);
memcpy(&mips->r[inst->dest], &mips->v[inst->src1], 4);
break;
case IROp::ExitToConst: