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3011 Commits
Author SHA1 Message Date
Henrik Rydgård e0634f3df9 Assorted cleanup and tweaks 2026-06-13 13:34:41 +02:00
fp64 2e290e0133 Fix VFPU dot bug 
Fix rounding-overflows-into-next-exponent bug in vdot pointed out in
https://github.com/hrydgard/ppsspp/issues/21070#issuecomment-4692749931
(unless I messed up again).
 2026-06-12 23:28:57 +03:00
fp64 3f154fb24e Implement (hopefully) bitwise-exact vmul/vdiv 
See https://github.com/hrydgard/ppsspp/issues/21070#issuecomment-4621393701
for details.

The implementation is not wired to anything currently, this is
just for reference purposes.

The alternative FTZ logic from
https://github.com/hrydgard/ppsspp/issues/21070#issuecomment-4642348708
is not implemented (i.e. this uses original double-based logic).

Also fixes space->tab for `vfpu_dot`.
 2026-06-11 16:40:06 +03:00
fp64 ef74666ac0 Fix style 2026-06-07 13:18:01 +03:00
fp64 cf7ff0044d Implement (hopefully) accurate vdot instruction 
Hopefully bitwise-exact to PSP.
See https://github.com/hrydgard/ppsspp/issues/21070#issuecomment-4640382516
for details.

Again, massive thanks to danzel for the data.

SIMD version not implemented.

Didn't touch USE_VFPU_DOT, etc., so needs to be enabled if you want
to test it.
 2026-06-07 12:24:44 +03:00
Herman SemenoffandHenrik Rydgård 29d4597108 IRFrontend: more optimize added +2 for downcount and pre-reserve after clear 2026-04-28 10:58:07 +02:00
Herman SemenoffandHenrik Rydgård 71cef62f96 mips/regcache: fix before check index after access data array by index 
This eliminates issues if it turns out that index can first receive data outside array

From #21608
 2026-04-28 10:55:55 +02:00
Henrik RydgårdandGitHub 5c082f8a2a Merge pull request #21499 from lrzlin/loong-handler 
loongarch: Implement excepetion handler and JIT bug fix
 2026-03-30 11:12:15 -06:00
Lin Runze 53338cf029 loongarch: Implement excepetion handler and JIT bug fix 2026-03-30 18:35:54 +08:00
Henrik Rydgård 0c077acc74 Do some include untangling, to limit the spread of the Windows.h include from SevenZipFileReader.h 2026-03-27 14:34:18 -06:00
Henrik Rydgård 55a255b042 Fix the ARM version of Vec4Pack32To8. 2026-03-26 10:49:32 -06:00
Henrik Rydgård 5a5630d130 More NEON/SSE in IRInterpreter 2026-03-26 10:49:32 -06:00
Henrik Rydgård 78739104b1 Additional micro-optimizations (verified) in the IRInterpreter 
Turns out that u8 promotes to int, causing signed indexing arithmetic
which is completely unnecessary.
 2026-03-26 10:49:32 -06:00
Henrik Rydgård b233745640 Add NEON versions of a few more IRInterpreter instructions 
Buildfix
 2026-03-26 10:49:32 -06:00
Henrik Rydgård 749e3a02cb Jit: Add missing instruction address check from ARM jits 2026-02-26 10:37:12 +01:00
Henrik Rydgård 1e57d8110f Minor blockcache improvement 2026-02-25 00:52:25 +01:00
Henrik RydgårdandGitHub d26a4a62ba Merge pull request #21282 from hrydgard/valgrind-fixes 
Fix a bunch of memory problems found by valgrind
 2026-02-19 12:35:31 +01:00
Henrik Rydgård 5a5c7028b9 Assorted warning fixes and data initialization to please valgrind 2026-02-19 11:24:46 +01:00
Henrik Rydgård 1c049b63d5 Throw in a safety check in JitBlockCache::DestroyBlock. 2026-02-19 00:30:39 +01:00
Henrik Rydgård 505a72bb3f Work around java exception seen in reporting. Buildfix. 2026-02-18 01:34:56 +01:00
Henrik Rydgård 8897b5914a Improve integrity checks in JIT (trying to catch an elusive crash) 2026-02-17 22:42:04 +01:00
Henrik Rydgård 1b0e701c87 Expose some more pointers in the ImDebugger UI 2026-02-17 22:40:00 +01:00
Henrik Rydgård f0ba391a4e Remove the whole concept of proxy blocks from the block cache, and experimental uses of it. 2026-02-17 09:40:27 +01:00
Henrik Rydgård 9f5be16663 Jit: Remove the Jal-to-replacement optimization (really not all that benificial) 2026-02-17 09:40:27 +01:00
Henrik Rydgård ca127b0e5b More fixes, more gamescreen button fixes 2026-02-12 01:35:57 +01:00
Henrik Rydgård 2797cfca56 Remove more vestiges of old experiments 2026-02-12 01:23:48 +01:00
Henrik Rydgård 44a2585753 Rename some function, remove an unused return value 2026-02-12 01:23:45 +01:00
Henrik Rydgård d5444a7f46 Remove old rudimentary start at a MIPS->MIPS jit 2026-02-11 23:33:41 +01:00
Henrik Rydgård b999c51a1a Code cleanup. Don't use gpr.SetRegImm where all we do is write to a scratch register 2026-02-10 19:28:53 +01:00
Henrik Rydgård e4f7a39c40 Correct an optimization in the ARM64 jit for min and max instructions 
Fixes the big glitch in #13444
 2026-02-10 19:28:53 +01:00
Henrik Rydgård 330a638281 Add ability to copy function hash from the disassembly view 
See #4179
 2026-02-09 19:26:43 +01:00
Henrik Rydgård 936c344a52 misc 2026-02-09 16:41:51 +01:00
Henrik Rydgård 4a8aeac38a Jit: Remove unused x86-only feature continueBranches. 2026-01-29 17:41:57 +01:00
Henrik Rydgård ed5a052258 Remove unused initial work for adding NEON support to ARM JITs. 
Our SIMD strategy for ARM is the JitUsingIR.
 2026-01-29 17:41:57 +01:00
Henrik Rydgård d6ebfed432 Fix some bugs and warnings from a pass of static analysis 2026-01-29 17:41:54 +01:00
刘皓 fde7821b77 Merge branch 'master' into libretro-vfs 2026-01-08 11:59:20 -05:00
fp64 ac22c45526 Fix vfpu_sin/vfpu_cos bug 
Was looking over VFPU stuff, and noticed this.
Presumably, on x86 the code was already doing exactly this, but still, ouch.

Did retest the code on all relevant (|x|>2^32) available inputs, all matches (except NaN payloads, as usual, but that is unrelated).
 2026-01-03 07:15:42 +02:00
刘皓 295ac0e9f6 Merge branch 'master' into libretro-vfs 2026-01-02 12:58:27 -05:00
Henrik Rydgård 8631e77db2 Delete some outdated profiler integrations 2026-01-01 13:55:30 +01:00
刘皓 5716cbd41d Use the libretro VFS interface in libretro builds 2026-01-01 00:24:01 -05:00
Henrik Rydgård 5f7a937466 Rename ValidSize to ClampValidSizeAt 2025-12-30 20:31:07 +01:00
Henrik Rydgård 1facc4d485 Remove obsolete hidden setting Browse 2025-11-04 23:39:56 +01:00
Henrik Rydgård c20be71c10 Fix the API for MIPSAssembleOpcode to remove a global 2025-11-03 16:08:07 +01:00
Henrik Rydgård 20e3a0cc70 Use temporaries to improve codegen in more IR vector ops 2025-10-17 09:26:15 +02:00
Henrik Rydgård d23a224e7a Use temporaries to try to improve codegen for IROp::Vec4Blend 2025-10-17 09:26:15 +02:00
Henrik Rydgård c3dfddebd7 IR interpreter: Improve code gen for the main interpreter loop 
Thanks to fp64 for the idea of using unreachable markers to avoid the
range check on the switch!

Additionally, use it in a few more places.
 2025-10-15 21:15:30 +02:00
Henrik Rydgård a170f40927 Qt buildfix 2025-10-10 08:45:09 -06:00
Henrik Rydgård a72fc6f79c Support showing (and sorting by) IR profiler info in the JIT viewer 
This will help future work on #19143 .
 2025-10-09 17:02:52 -06:00
Henrik Rydgård db0cc01a81 IR interpreter on ARM64: Cleanup FPCR set/get, support floating point control on Windows 2025-10-09 11:14:47 -06:00
Henrik Rydgård ff5dea821b New jit viewer is starting to work a bit. 2025-10-08 16:59:25 -06:00