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685 Commits
Author SHA1 Message Date
Unknown W. Brackets 5d2ff64252 Support for modified jit-enabled VerySleepy. 
This allows profiling the jit.  Should have zero perf impact when not
in use, since it's entirely triggered by VerySleepy.
 2013-11-30 19:20:21 -08:00
Henrik Rydgard 23e57b71e0 Revert "Shave one instruction off slti and slt on ARM." 
This reverts commit 04742e00fc.
 2013-11-30 16:06:16 +01:00
Henrik Rydgard 04742e00fc Shave one instruction off slti and slt on ARM. 2013-11-30 15:53:21 +01:00
Unknown W. Brackets dffa35ef2f When ins is used with a zero argument, don't OR. 
Seems it's used effectively to mask out bits with rs=zero.  Makes sense...
 2013-11-29 09:17:12 -08:00
Sacha 90b5097d45 Travis: add Blackberry. Improve Blackberry out-of-box compile. 2013-11-29 00:18:41 +10:00
Henrik Rydgard 55500d4bb6 Reorder VFPU registers in memory so that we can flush and reload them in bulk more often. 
Doesn't actually do that yet, that's for the NEON branch.
 2013-11-28 13:27:51 +01:00
Henrik Rydgard e5e23f3ce1 ARM: Fix vsgn. Some vertex decoder tweaks. 2013-11-24 18:21:47 +01:00
Henrik Rydgard 030e6460cc ARM: NEON-optimize software skinning 2013-11-24 18:03:42 +01:00
Henrik Rydgard f650b23c90 ARM: Add NEON widening and narrowing moves, and float/int convert. 
Experiment a little in the vertex decoder.
 2013-11-24 13:30:28 +01:00
Henrik Rydgard db016f7001 ARMJIT: Disable vsgn, reported to break Miami Vice 2013-11-23 13:00:35 +01:00
Unknown W. Brackets c50ab6d6aa armjit: Fix divu when divisor is a constant 1. 
Fixes #4539 and #4520.
 2013-11-19 13:24:15 -08:00
Henrik Rydgard bd3a03ad1d Quick buildfix. Last commit was meant to go on a WIP branch but meh :) 2013-11-19 21:44:18 +01:00
Henrik Rydgard ab3037112f Some scaffolding for a future VFPU-on-NEON implementation 2013-11-19 21:41:48 +01:00
Henrik Rydgard 99af10cb09 Get rid of bool disablePrefixes in ARM build (already gone in x86) 2013-11-19 21:41:48 +01:00
Henrik Rydgard dca457e6df Optimize multiple sv.s and lv.s calls on ARM. Also some cleanup. 2013-11-19 21:41:47 +01:00
Henrik Rydgard 5bb3824dcf Implement vocp on ARM and x86. 2013-11-19 21:41:47 +01:00
Henrik Rydgard 9f5402ce54 Use hardware half-to-float on ARM when available. 2013-11-17 14:17:13 +01:00
Henrik Rydgard 4e0520131a Tiny optimization 2013-11-15 20:32:23 +01:00
Henrik Rydgard d17a5fefea ARM: Fix divide by 0 in software divide used on CPUs without HW divide. 2013-11-15 20:24:20 +01:00
Unknown W. Brackets 5128083d93 Mask out fcr31 bits that can't be set on a PSP. 2013-11-14 23:57:28 -08:00
Unknown W. Brackets 3c73d0d1f1 armjit: Read fpu control regs other than 0/31 as 0. 
Always seem to give zero, regardless of the value of fcr31, etc.
 2013-11-14 23:39:39 -08:00
Unknown W. Brackets 763eff181d Fix handling of jalr when delay slot changes rd. 2013-11-14 23:39:13 -08:00
Unknown W. Brackets 26f5922174 Return the correct value for fcr0/fir. 
This is what the PSP actually returns, it's read only.
 2013-11-14 23:39:08 -08:00
Unknown W. Brackets 98fb2e0402 armjit: Refer to R11 as MEMBASEREG for clarity. 2013-11-14 23:37:48 -08:00
Sacha e3bdb3e09b Disable LitPool as it is causing crashes with Vertex Decoder JIT. Performance seems to be almost unaffected since the IMM changes. 2013-11-15 14:12:00 +10:00
Sacha 20e8a81268 Switch to compile-time ARMV7 define. 2013-11-15 11:20:39 +10:00
Henrik Rydgard 9a14d33372 Disable software divide that appears to be buggy, see #4539 2013-11-14 17:25:02 +01:00
Henrik Rydgård ef8631c57f Cache VFPU_CTRL_CC in a register 2013-11-12 17:58:29 +01:00
Henrik Rydgard df3765a320 Arm jit: optimize ES, NS conditions in vcmp. Bugfix TR. 2013-11-12 14:43:12 +01:00
Unknown W. Brackets f4b5e8a4c1 Merge pull request #4518 from hrydgard/fpcond 
ARMJIT: Cache fpcond in a register to avoid store/load between compare and branch
 2013-11-12 01:50:16 -08:00
Henrik Rydgård 17074f5a7f Cache fpcond in a register to avoid store/load between compare and branch 2013-11-12 10:33:38 +01:00
Unknown W. Brackets 32504ed46e armjit: Prioritize spilling regs not used soon. 
This may improve trashing.
 2013-11-12 00:03:39 -08:00
Unknown W. Brackets 1bfce12fdd armjit: Report some unexpected situations. 2013-11-11 23:41:18 -08:00
Unknown W. Brackets ac5aacbd16 armjit: Spill an imm armreg back to an imm. 
We might be able to avoid the store or etc.
 2013-11-11 23:39:13 -08:00
Unknown W. Brackets bb960480c8 x86/armjit: Stop compiling on a jump to invalid. 2013-11-10 21:59:50 -08:00
Unknown W. Brackets 359110f010 x86/armjit: Add jump following (off by default.) 
Inlines function calls up to a certain extent.  Allows us to get
immediates all the way to a syscall, for example, usually.

Not sure if faster.
 2013-11-10 21:59:49 -08:00
Unknown W. Brackets aacb31bc18 armjit: Copy over (disabled) immbranch optim. 
This does a little loop unrolling.  Costs a bit more cache space, but
avoids flushing regs for longer.

Not enabled.
 2013-11-10 21:59:48 -08:00
Unknown W. Brackets 92ecff4396 armjit: keep track of instructions in jitstate. 
To match x86.
 2013-11-10 21:59:48 -08:00
Unknown W. Brackets 8ceaafc159 armjit: Verify free space while compiling. 2013-11-10 21:59:48 -08:00
Unknown W. Brackets ca7b2b554b armjit: fix major typo breaking mult/multu. 2013-11-10 21:54:44 -08:00
Unknown W. Brackets e1fffdb37a armjit: Don't reload an armreg ptr marked noinit. 2013-11-10 16:43:38 -08:00
Unknown W. Brackets 67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
Unknown W. Brackets bc0a846475 armjit: Optimize imm addresses (could do better...) 2013-11-10 16:30:20 -08:00
Unknown W. Brackets c63560c0dd armjit: Try to find imms to optimize a reg load. 
This way we skip the MOVW/MOVT and go for one op only.
 2013-11-10 16:20:34 -08:00
Unknown W. Brackets 7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00
Unknown W. Brackets d092f7dd2d armjit: Remember reg imm values even after flush. 
This way, we can base other imm values off them, or even do imm math using
them.  We can also avoid re-flushing an imm.
 2013-11-10 15:50:14 -08:00
Unknown W. Brackets 7f9cbc0f10 armjit: Minor cleanup and logging tweaks. 2013-11-10 15:12:40 -08:00
Unknown W. Brackets 455a7e090d Compile the cache instruction to nothing. 
Was showing up in a few profiles, does nothing currently.
 2013-11-10 14:38:10 -08:00
Unknown W. Brackets 1cc68f50ca armjit: Small optimization to syscall instr. 2013-11-10 14:38:10 -08:00
Unknown W. Brackets b30928036e armjit: Avoid flushing an imm in beq/bne/etc. 
We might be able to STMIA it instead.
 2013-11-10 14:38:10 -08:00