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Optimize multiple sv.s and lv.s calls on ARM. Also some cleanup.

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This commit is contained in:
Henrik Rydgard
2013-11-19 21:41:47 +01:00
parent 5bb3824dcf
commit dca457e6df
3 changed files with 26 additions and 14 deletions
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Core/MIPS/ARM/ArmCompVFPU.cpp
+20 -8
View File
@@ -241,7 +241,7 @@ namespace MIPSComp
void Jit::Comp_SV(MIPSOpcode op) {
CONDITIONAL_DISABLE;
s32 imm = (signed short)(op&0xFFFC);
s32 offset = (signed short)(op & 0xFFFC);
int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
MIPSGPReg rs = _RS;
@@ -250,19 +250,24 @@ namespace MIPSComp
{
case 50: //lv.s // VI(vt) = Memory::Read_U32(addr);
{
// TODO: Fastpath like FPULS.
if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {
gpr.MapRegAsPointer(rs);
fpr.MapRegV(vt, MAP_NOINIT | MAP_DIRTY);
VLDR(fpr.V(vt), gpr.RPtr(rs), offset);
break;
}
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt, MAP_DIRTY | MAP_NOINIT);
if (gpr.IsImm(rs)) {
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(R0, addr + (u32)Memory::base);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
SetR0ToEffectiveAddress(rs, imm);
SetR0ToEffectiveAddress(rs, offset);
} else {
SetCCAndR0ForSafeAddress(rs, imm, R1);
SetCCAndR0ForSafeAddress(rs, offset, R1);
doCheck = true;
}
ADD(R0, R0, MEMBASEREG);
@@ -290,17 +295,24 @@ namespace MIPSComp
case 58: //sv.s // Memory::Write_U32(VI(vt), addr);
{
if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) {
gpr.MapRegAsPointer(rs);
fpr.MapRegV(vt, 0);
VSTR(fpr.V(vt), gpr.RPtr(rs), offset);
break;
}
// CC might be set by slow path below, so load regs first.
fpr.MapRegV(vt);
if (gpr.IsImm(rs)) {
u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF;
u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
gpr.SetRegImm(R0, addr + (u32)Memory::base);
} else {
gpr.MapReg(rs);
if (g_Config.bFastMemory) {
SetR0ToEffectiveAddress(rs, imm);
SetR0ToEffectiveAddress(rs, offset);
} else {
SetCCAndR0ForSafeAddress(rs, imm, R1);
SetCCAndR0ForSafeAddress(rs, offset, R1);
doCheck = true;
}
ADD(R0, R0, MEMBASEREG);
Core/MIPS/ARM/ArmJit.cpp
+5 -6
View File
@@ -372,12 +372,12 @@ void Jit::MovToPC(ARMReg r) {
void Jit::SaveDowncount() {
if (jo.downcountInRegister)
STR(R7, CTXREG, offsetof(MIPSState, downcount));
STR(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
}
void Jit::RestoreDowncount() {
if (jo.downcountInRegister)
LDR(R7, CTXREG, offsetof(MIPSState, downcount));
LDR(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
}
void Jit::WriteDownCount(int offset)
@@ -386,12 +386,12 @@ void Jit::WriteDownCount(int offset)
int theDowncount = js.downcountAmount + offset;
Operand2 op2;
if (TryMakeOperand2(theDowncount, op2)) {
SUBS(R7, R7, op2);
SUBS(DOWNCOUNTREG, DOWNCOUNTREG, op2);
} else {
// Should be fine to use R2 here, flushed the regcache anyway.
// If js.downcountAmount can be expressed as an Imm8, we don't need this anyway.
gpr.SetRegImm(R2, theDowncount);
SUBS(R7, R7, R2);
SUBS(DOWNCOUNTREG, DOWNCOUNTREG, R2);
}
} else {
int theDowncount = js.downcountAmount + offset;
@@ -399,14 +399,13 @@ void Jit::WriteDownCount(int offset)
Operand2 op2;
if (TryMakeOperand2(theDowncount, op2)) {
SUBS(R1, R1, op2);
STR(R1, CTXREG, offsetof(MIPSState, downcount));
} else {
// Should be fine to use R2 here, flushed the regcache anyway.
// If js.downcountAmount can be expressed as an Imm8, we don't need this anyway.
gpr.SetRegImm(R2, theDowncount);
SUBS(R1, R1, R2);
STR(R1, CTXREG, offsetof(MIPSState, downcount));
}
STR(R1, CTXREG, offsetof(MIPSState, downcount));
}
}
Core/MIPS/ARM/ArmRegCache.h
+1
View File
@@ -25,6 +25,7 @@ using namespace ArmGen;
#define CTXREG (R10)
#define MEMBASEREG (R11)
#define DOWNCOUNTREG (R7)
// R2 to R8: mapped MIPS regs
// R9 = code pointers