Add an invalidate all method to the jit.

Core/Debugger/Breakpoints.cpp

@@ -413,9 +413,9 @@ void CBreakPoints::Update(u32 addr)
 		
 		// In case this is a delay slot, clear the previous instruction too.
 		if (addr != 0)
-			MIPSComp::jit->ClearCacheAt(addr - 4, 8);
+			MIPSComp::jit->InvalidateCacheAt(addr - 4, 8);
 		else
-			MIPSComp::jit->ClearCache();
+			MIPSComp::jit->InvalidateCache();
 
 		if (resume)
 			Core_EnableStepping(false);

Core/HLE/sceKernel.cpp

@@ -364,11 +364,8 @@ int sceKernelDcacheInvalidateRange(u32 addr, int size)
 }
 
 int sceKernelIcacheInvalidateRange(u32 addr, int size) {
-	DEBUG_LOG(CPU,"sceKernelIcacheInvalidateRange(%08x, %i)", addr, size);
-	// TODO: Make the JIT hash and compare the touched blocks.
-	if(MIPSComp::jit){
-		MIPSComp::jit->ClearCacheAt(addr, size);
-	}
+	DEBUG_LOG(CPU, "sceKernelIcacheInvalidateRange(%08x, %i)", addr, size);
+	currentMIPS->InvalidateICache(addr, size);
 	return 0;
 }
 

Core/MIPS/ARM/ArmJit.cpp

@@ -146,7 +146,12 @@ void Jit::ClearCache()
 	GenerateFixedCode();
 }
 
-void Jit::ClearCacheAt(u32 em_address, int length)
+void Jit::InvalidateCache()
+{
+	blocks.Clear();
+}
+
+void Jit::InvalidateCacheAt(u32 em_address, int length)
 {
 	blocks.InvalidateICache(em_address, length);
 }

Core/MIPS/ARM/ArmJit.h

@@ -178,7 +178,8 @@ public:
 	JitBlockCache *GetBlockCache() { return &blocks; }
 
 	void ClearCache();
-	void ClearCacheAt(u32 em_address, int length = 4);
+	void InvalidateCache();
+	void InvalidateCacheAt(u32 em_address, int length = 4);
 
 	void EatPrefix() { js.EatPrefix(); }
 

Core/MIPS/MIPS.cpp

@@ -328,5 +328,5 @@ u32 MIPSState::ReadFCR(int reg) {
 void MIPSState::InvalidateICache(u32 address, int length) {
 	// Only really applies to jit.
 	if (MIPSComp::jit)
-		MIPSComp::jit->ClearCacheAt(address, length);
+		MIPSComp::jit->InvalidateCacheAt(address, length);
 }

Core/MIPS/MIPSInt.cpp

@@ -133,7 +133,7 @@ namespace MIPSInt
 		case 8:
 			// Invalidate the instruction cache at this address
 			if (MIPSComp::jit) {
-				MIPSComp::jit->ClearCacheAt(addr, 0x40);
+				MIPSComp::jit->InvalidateCacheAt(addr, 0x40);
 			}
 			break;
 

Core/MIPS/PPC/PpcJit.cpp

@@ -217,7 +217,11 @@ void Jit::ClearCache() {
 	GenerateFixedCode();
 }
 
-void Jit::ClearCacheAt(u32 em_address, int length) {
+void Jit::InvalidateCache() {
+	blocks.Clear();
+}
+
+void Jit::InvalidateCacheAt(u32 em_address, int length) {
 	blocks.InvalidateICache(em_address, length);
 }
 

Core/MIPS/PPC/PpcJit.h

@@ -286,7 +286,8 @@ namespace MIPSComp
 		void WriteSyscallExit();
 
 		void ClearCache();
-		void ClearCacheAt(u32 em_address, int length = 4);
+		void InvalidateCache();
+		void InvalidateCacheAt(u32 em_address, int length = 4);
 
 		void RunLoopUntil(u64 globalticks);
 		void GenerateFixedCode();

Core/MIPS/x86/Jit.cpp

@@ -218,7 +218,12 @@ void Jit::ClearCache()
 	ClearCodeSpace();
 }
 
-void Jit::ClearCacheAt(u32 em_address, int length)
+void Jit::InvalidateCache()
+{
+	blocks.Clear();
+}
+
+void Jit::InvalidateCacheAt(u32 em_address, int length)
 {
 	blocks.InvalidateICache(em_address, length);
 }

Core/MIPS/x86/Jit.h

@@ -168,7 +168,8 @@ public:
 	AsmRoutineManager &Asm() { return asm_; }
 
 	void ClearCache();
-	void ClearCacheAt(u32 em_address, int length = 4);
+	void InvalidateCache();
+	void InvalidateCacheAt(u32 em_address, int length = 4);
 
 private:
 	void GetStateAndFlushAll(RegCacheState &state);

Windows/Debugger/CtrlDisAsmView.cpp

@@ -298,7 +298,7 @@ void CtrlDisAsmView::assembleOpcode(u32 address, std::string defaultText)
 		Memory::Write_U32(encoded, address);
 		// In case this is a delay slot or combined instruction, clear cache above it too.
 		if (MIPSComp::jit)
-			MIPSComp::jit->ClearCacheAt(address - 4, 8);
+			MIPSComp::jit->InvalidateCacheAt(address - 4, 8);
 		scanFunctions();
 
 		if (address == curAddress)