From da212fb33e20c6d091111a75eaec614e67338ed7 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Thu, 19 Jun 2014 01:08:45 -0700 Subject: [PATCH] Add an invalidate all method to the jit. --- Core/Debugger/Breakpoints.cpp | 4 ++-- Core/HLE/sceKernel.cpp | 7 ++----- Core/MIPS/ARM/ArmJit.cpp | 7 ++++++- Core/MIPS/ARM/ArmJit.h | 3 ++- Core/MIPS/MIPS.cpp | 2 +- Core/MIPS/MIPSInt.cpp | 2 +- Core/MIPS/PPC/PpcJit.cpp | 6 +++++- Core/MIPS/PPC/PpcJit.h | 3 ++- Core/MIPS/x86/Jit.cpp | 7 ++++++- Core/MIPS/x86/Jit.h | 3 ++- Windows/Debugger/CtrlDisAsmView.cpp | 2 +- 11 files changed, 30 insertions(+), 16 deletions(-) diff --git a/Core/Debugger/Breakpoints.cpp b/Core/Debugger/Breakpoints.cpp index 893714792a..785baa8927 100644 --- a/Core/Debugger/Breakpoints.cpp +++ b/Core/Debugger/Breakpoints.cpp @@ -413,9 +413,9 @@ void CBreakPoints::Update(u32 addr) // In case this is a delay slot, clear the previous instruction too. if (addr != 0) - MIPSComp::jit->ClearCacheAt(addr - 4, 8); + MIPSComp::jit->InvalidateCacheAt(addr - 4, 8); else - MIPSComp::jit->ClearCache(); + MIPSComp::jit->InvalidateCache(); if (resume) Core_EnableStepping(false); diff --git a/Core/HLE/sceKernel.cpp b/Core/HLE/sceKernel.cpp index 72b9b8d1a1..31c6584932 100644 --- a/Core/HLE/sceKernel.cpp +++ b/Core/HLE/sceKernel.cpp @@ -364,11 +364,8 @@ int sceKernelDcacheInvalidateRange(u32 addr, int size) } int sceKernelIcacheInvalidateRange(u32 addr, int size) { - DEBUG_LOG(CPU,"sceKernelIcacheInvalidateRange(%08x, %i)", addr, size); - // TODO: Make the JIT hash and compare the touched blocks. - if(MIPSComp::jit){ - MIPSComp::jit->ClearCacheAt(addr, size); - } + DEBUG_LOG(CPU, "sceKernelIcacheInvalidateRange(%08x, %i)", addr, size); + currentMIPS->InvalidateICache(addr, size); return 0; } diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index 1a69978a09..f4b736b6a7 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -146,7 +146,12 @@ void Jit::ClearCache() GenerateFixedCode(); } -void Jit::ClearCacheAt(u32 em_address, int length) +void Jit::InvalidateCache() +{ + blocks.Clear(); +} + +void Jit::InvalidateCacheAt(u32 em_address, int length) { blocks.InvalidateICache(em_address, length); } diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h index 8595d6d527..ef254319f4 100644 --- a/Core/MIPS/ARM/ArmJit.h +++ b/Core/MIPS/ARM/ArmJit.h @@ -178,7 +178,8 @@ public: JitBlockCache *GetBlockCache() { return &blocks; } void ClearCache(); - void ClearCacheAt(u32 em_address, int length = 4); + void InvalidateCache(); + void InvalidateCacheAt(u32 em_address, int length = 4); void EatPrefix() { js.EatPrefix(); } diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp index e8ffb19b71..a59e4d0382 100644 --- a/Core/MIPS/MIPS.cpp +++ b/Core/MIPS/MIPS.cpp @@ -328,5 +328,5 @@ u32 MIPSState::ReadFCR(int reg) { void MIPSState::InvalidateICache(u32 address, int length) { // Only really applies to jit. if (MIPSComp::jit) - MIPSComp::jit->ClearCacheAt(address, length); + MIPSComp::jit->InvalidateCacheAt(address, length); } diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index 602ee61f67..9a555b7d9a 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -133,7 +133,7 @@ namespace MIPSInt case 8: // Invalidate the instruction cache at this address if (MIPSComp::jit) { - MIPSComp::jit->ClearCacheAt(addr, 0x40); + MIPSComp::jit->InvalidateCacheAt(addr, 0x40); } break; diff --git a/Core/MIPS/PPC/PpcJit.cpp b/Core/MIPS/PPC/PpcJit.cpp index 8e4c67b6c6..583de42661 100644 --- a/Core/MIPS/PPC/PpcJit.cpp +++ b/Core/MIPS/PPC/PpcJit.cpp @@ -217,7 +217,11 @@ void Jit::ClearCache() { GenerateFixedCode(); } -void Jit::ClearCacheAt(u32 em_address, int length) { +void Jit::InvalidateCache() { + blocks.Clear(); +} + +void Jit::InvalidateCacheAt(u32 em_address, int length) { blocks.InvalidateICache(em_address, length); } diff --git a/Core/MIPS/PPC/PpcJit.h b/Core/MIPS/PPC/PpcJit.h index 19d98378d0..4f88017b72 100644 --- a/Core/MIPS/PPC/PpcJit.h +++ b/Core/MIPS/PPC/PpcJit.h @@ -286,7 +286,8 @@ namespace MIPSComp void WriteSyscallExit(); void ClearCache(); - void ClearCacheAt(u32 em_address, int length = 4); + void InvalidateCache(); + void InvalidateCacheAt(u32 em_address, int length = 4); void RunLoopUntil(u64 globalticks); void GenerateFixedCode(); diff --git a/Core/MIPS/x86/Jit.cpp b/Core/MIPS/x86/Jit.cpp index 66606e2635..d7a04fe350 100644 --- a/Core/MIPS/x86/Jit.cpp +++ b/Core/MIPS/x86/Jit.cpp @@ -218,7 +218,12 @@ void Jit::ClearCache() ClearCodeSpace(); } -void Jit::ClearCacheAt(u32 em_address, int length) +void Jit::InvalidateCache() +{ + blocks.Clear(); +} + +void Jit::InvalidateCacheAt(u32 em_address, int length) { blocks.InvalidateICache(em_address, length); } diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h index 8fda662e61..c210ef6fc6 100644 --- a/Core/MIPS/x86/Jit.h +++ b/Core/MIPS/x86/Jit.h @@ -168,7 +168,8 @@ public: AsmRoutineManager &Asm() { return asm_; } void ClearCache(); - void ClearCacheAt(u32 em_address, int length = 4); + void InvalidateCache(); + void InvalidateCacheAt(u32 em_address, int length = 4); private: void GetStateAndFlushAll(RegCacheState &state); diff --git a/Windows/Debugger/CtrlDisAsmView.cpp b/Windows/Debugger/CtrlDisAsmView.cpp index e205b93ec5..61dfd8e221 100644 --- a/Windows/Debugger/CtrlDisAsmView.cpp +++ b/Windows/Debugger/CtrlDisAsmView.cpp @@ -298,7 +298,7 @@ void CtrlDisAsmView::assembleOpcode(u32 address, std::string defaultText) Memory::Write_U32(encoded, address); // In case this is a delay slot or combined instruction, clear cache above it too. if (MIPSComp::jit) - MIPSComp::jit->ClearCacheAt(address - 4, 8); + MIPSComp::jit->InvalidateCacheAt(address - 4, 8); scanFunctions(); if (address == curAddress)