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arm64jit: Avoid spilling an extra reg for lwl/lwr.

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It's only needed for swl and swr.
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Unknown W. Brackets committed 2018-01-01 08:38:10 -08:00
1 parent 8ffb0101fe
commit d8d174fa2b
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Core/MIPS/ARM64/Arm64CompLoadStore.cpp
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@@ -180,7 +180,7 @@ namespace MIPSComp {
gpr.SpillLock(rs);
// Need to get temps before skipping safe mem.
ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR();
ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR();
ARM64Reg LR_SCRATCH4 = o == 42 || o == 46 ? gpr.GetAndLockTempR() : INVALID_REG;
if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);