From d8d174fa2b34bb23bbe42eceee514d0decbcc89d Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Sun, 31 Dec 2017 16:39:11 -0800
Subject: [PATCH] arm64jit: Avoid spilling an extra reg for lwl/lwr.

It's only needed for swl and swr.
---
 Core/MIPS/ARM64/Arm64CompLoadStore.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
index a3f44e9e89..9a226a32e6 100644
--- a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
+++ b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp
@@ -180,7 +180,7 @@ namespace MIPSComp {
 		gpr.SpillLock(rs);
 		// Need to get temps before skipping safe mem.
 		ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR();
-		ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR();
+		ARM64Reg LR_SCRATCH4 = o == 42 || o == 46 ? gpr.GetAndLockTempR() : INVALID_REG;
 
 		if (!g_Config.bFastMemory && rs != MIPS_REG_SP) {
 			skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);