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10
Commits
v0.8.2
...
n64-systemtest
| Author | SHA1 | Date | |
|---|---|---|---|
 Rosalie Wanders
|
cd89473f7e | ||
|
Rosalie Wanders
|
b89fed20e8 | ||
|
Rosalie Wanders
|
28af6a436e | ||
|
Rosalie Wanders
|
9c53a846b8 | ||
|
Rosalie Wanders
|
816bb4c426 | ||
|
Rosalie Wanders
|
c119e5f128 | ||
|
Rosalie Wanders
|
d64b23bdfe | ||
|
Rosalie Wanders
|
b03f118b04 | ||
|
Rosalie Wanders
|
d18ac4076f | ||
|
Rosalie Wanders
|
4620c1beb8 |
@@ -1,6 +1,6 @@
|
||||
# Maintainer: Rosalie Wanders <rosalie@mailbox.org>
|
||||
pkgname=rmg
|
||||
pkgver=0.8.2
|
||||
pkgver=0.8.3
|
||||
pkgrel=1
|
||||
pkgdesc="Rosalie's Mupen GUI"
|
||||
arch=('x86_64' 'aarch64')
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
Name: RMG
|
||||
Version: 0.8.2
|
||||
Version: 0.8.3
|
||||
Release: %autorelease
|
||||
Summary: Rosalie's Mupen GUI
|
||||
|
||||
|
||||
@@ -29,6 +29,18 @@
|
||||
</screenshot>
|
||||
</screenshots>
|
||||
<releases>
|
||||
<release version="v0.8.3" date="2025-09-28" type="stable">
|
||||
<description>
|
||||
<p>Changes:</p>
|
||||
<ul>
|
||||
<li>Fix supported 64DD games not having the transfer pak functionality enabled</li>
|
||||
<li>Fix crash in Mario Artist Talent Studio when using mupen64plus-rsp-hle since v0.8.2</li>
|
||||
<li>Fix frame count not increasing from 0 since v0.8.2</li>
|
||||
<li>Fix loading save states freezing since v0.8.2</li>
|
||||
<li>Add clear buttons to 64DD IPL settings in the settings dialog</li>
|
||||
</ul>
|
||||
</description>
|
||||
</release>
|
||||
<release version="v0.8.2" date="2025-09-26" type="stable">
|
||||
<description>
|
||||
<p>Changes:</p>
|
||||
|
||||
+53
-14
@@ -6130,18 +6130,6 @@ RefMD5=70C525880240C1E838B8B1BE35666C3B
|
||||
GoodName=GoldenEye 007 Intro by SonCrap (PD)
|
||||
CRC=9303DD17 0813B398
|
||||
|
||||
[67F2E18ED18A5F0EA3FE2D913E3F1786]
|
||||
GoodName=GoldenEye X
|
||||
; Alternate Title=GoldenEye X (5e Clouds)
|
||||
CRC=FDF95D15 618546CA
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[435D75D07878D305293EC4D591B86303]
|
||||
GoodName=GoldenEye X
|
||||
; Alternate Title=GoldenEye X (5e Cloudless)
|
||||
CRC=E8B3F63D E5A997B1
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[EA0E3E6AEFA58738A12906298373218B]
|
||||
GoodName=GoldenEye 007 (UE) (Switch Online) [!]
|
||||
CRC=DCBC50D1 9FD1AA3
|
||||
@@ -12024,10 +12012,25 @@ Rumble=Yes
|
||||
Transferpak=Yes
|
||||
|
||||
[5D72155E00Bf2CAB41B0F4A2f2E09C61]
|
||||
GoodName=Perfect Dark Plus
|
||||
GoodName=Perfect Dark Plus [h1]
|
||||
CRC=FB453D58 AD565422
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[67F2E18ED18A5F0EA3FE2D913E3F1786]
|
||||
GoodName=GoldenEye X [h2] (5e Clouds)
|
||||
CRC=FDF95D15 618546CA
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[435D75D07878D305293EC4D591B86303]
|
||||
GoodName=GoldenEye X [h3] (5e Cloudless)
|
||||
CRC=E8B3F63D E5A997B1
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[640923B68B9281044AC1B518612E979B]
|
||||
GoodName=GoldenEye X [h4] (6a)
|
||||
CRC=BE0052C3 2CA8CFB2
|
||||
RefMD5=E03B088B6AC9E0080440EFED07C1E40F
|
||||
|
||||
[E0BCB2758EDF0AC6AB7DB36D98E1E57C]
|
||||
GoodName=Pikachu Genki Dechu (J) [!]
|
||||
CRC=3F245305 FC0B74AA
|
||||
@@ -14372,6 +14375,11 @@ GoodName=Space Station Silicon Valley (E) (M7) [b1]
|
||||
CRC=FC70E272 08FFE7AA
|
||||
RefMD5=FCA7AFCADCF5E5545A62919BA94DAD18
|
||||
|
||||
[2E91FFB252AA28B99E82D8F74BCC3831]
|
||||
GoodName=Space Station Silicon Valley (E) (M7) [f1] (FBM Fix v1.2)
|
||||
CRC=FC70E272 08FFE7AA
|
||||
RefMD5=FCA7AFCADCF5E5545A62919BA94DAD18
|
||||
|
||||
[E66ED1CC4AB95D0872BB2EBC49B206C4]
|
||||
GoodName=Space Station Silicon Valley (J) [!]
|
||||
CRC=BFE23884 EF48EAAF
|
||||
@@ -14379,6 +14387,11 @@ Players=1
|
||||
SaveType=Eeprom 4KB
|
||||
Rumble=Yes
|
||||
|
||||
[042D1CBD3F4705642D12D004F0649558]
|
||||
GoodName=Space Station Silicon Valley (J) [f1] (ExpFBM Fix v1.2)
|
||||
CRC=7AB86C9B A6487448
|
||||
RefMD5=E66ED1CC4AB95D0872BB2EBC49B206C4
|
||||
|
||||
[868B37D1B66D1D994E2BAD4E218BF129]
|
||||
GoodName=Space Station Silicon Valley (U) [!]
|
||||
CRC=BFE23884 EF48EAAF
|
||||
@@ -14396,13 +14409,23 @@ GoodName=Space Station Silicon Valley (U) [f2] (PAL)
|
||||
CRC=BFE23884 EF48EAAF
|
||||
RefMD5=868B37D1B66D1D994E2BAD4E218BF129
|
||||
|
||||
[92EE9AF3DFEB19A1339F3C75BAED1E6B]
|
||||
GoodName=Space Station Silicon Valley (U) (M7) [f3] (ExpFBMLSelect Fix v1.2)
|
||||
CRC=7AB86C9D 37CD109C
|
||||
RefMD5=868B37D1B66D1D994E2BAD4E218BF129
|
||||
|
||||
[F1F1C5E2B895DB63348BC738C0CDC645]
|
||||
GoodName=Space Station Silicon Valley (U) (V1.1) [!]
|
||||
CRC=FC70E272 8FFE7AA
|
||||
CRC=FC70E272 08FFE7AA
|
||||
Players=1
|
||||
SaveType=Eeprom 4KB
|
||||
Rumble=Yes
|
||||
|
||||
[9325E39AF74FC9571B5F2EFFCC1676A9]
|
||||
GoodName=Space Station Silicon Valley (U) (V1.1) (M7) [f1] (FBMLSelect Fix v1.2)
|
||||
CRC=FC70E270 658EA161
|
||||
RefMD5=F1F1C5E2B895DB63348BC738C0CDC645
|
||||
|
||||
[630E4122B0743A29C246DA2C257F92DA]
|
||||
GoodName=Spacer by Memir (POM '99) (PD)
|
||||
CRC=A3A044B5 6DB1BF5E
|
||||
@@ -18329,9 +18352,19 @@ GoodName=64DD IPL (USA)
|
||||
|
||||
[8485643E5830CD67ED4C0A5FD49E2491]
|
||||
GoodName=Mario Artist Paint Studio (J)
|
||||
Transferpak=Yes
|
||||
|
||||
[B17771664DAF95D7E61D8549A8CEACC6]
|
||||
GoodName=Mario Artist Paint Studio (J) [English v2.1]
|
||||
Transferpak=Yes
|
||||
|
||||
[88228E990B58A94E9B3460BEFF632304]
|
||||
GoodName=Mario Artist Talent Studio (J)
|
||||
Transferpak=Yes
|
||||
|
||||
[F3767735B1610C2BCA3220B590D43232]
|
||||
GoodName=Mario Artist Talent Studio (J) [English v2.1]
|
||||
Transferpak=Yes
|
||||
|
||||
[114AF722029D6386C3BFEA4CC8FA603C]
|
||||
GoodName=Mario Artist Communication Kit (J)
|
||||
@@ -18339,9 +18372,15 @@ GoodName=Mario Artist Communication Kit (J)
|
||||
[DA23EE561578B7DAD77ED72728B46D30]
|
||||
GoodName=Mario Artist Polygon Studio (J)
|
||||
|
||||
[7B94CB9AF6FE351CA7B47F59594AF96C]
|
||||
GoodName=Mario Artist Polygon Studio (J) [English v3.0]
|
||||
|
||||
[EBBA03F20096FC2BC178FC3A1F4EC2B6]
|
||||
GoodName=Sim City 64 (J)
|
||||
|
||||
[4372F74477FE54CD363FE4F14984625A]
|
||||
GoodName=Sim City 64 (J) [English v0.6.38]
|
||||
|
||||
[9F797A9C704B5EBD04D6A2B036309AF2]
|
||||
GoodName=Nihon Pro Golf Tour 64 (J)
|
||||
|
||||
|
||||
+1
-1
@@ -253,7 +253,7 @@ ifeq ($(OS), OSX)
|
||||
endif
|
||||
ifeq ($(OS), MINGW)
|
||||
TARGET = mupen64plus$(POSTFIX).dll
|
||||
ifeq ($(CC), clang)
|
||||
ifeq (clang, $(word 1, $(shell $(CC) --version)))
|
||||
LDFLAGS += -shared -Wl,-export-all-symbols
|
||||
else
|
||||
LDFLAGS += -Wl,-Bsymbolic -shared -Wl,-export-all-symbols
|
||||
|
||||
@@ -58,7 +58,7 @@ void pif_bootrom_hle_execute(struct r4300_core* r4300)
|
||||
unsigned int tv_type = get_tv_type(); /* 0:PAL, 1:NTSC, 2:MPAL */
|
||||
|
||||
int64_t* r4300_gpregs = r4300_regs(r4300);
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
/* setup CP0 registers */
|
||||
cp0_regs[CP0_STATUS_REG] = 0x34000000;
|
||||
|
||||
@@ -136,7 +136,7 @@ void cached_interp_##name##_OUT(void) \
|
||||
void cached_interp_##name##_IDLE(void) \
|
||||
{ \
|
||||
DECLARE_R4300 \
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0); \
|
||||
const int take_jump = (condition); \
|
||||
if (cop1 && check_cop1_unusable(r4300)) return; \
|
||||
|
||||
+11
-11
@@ -49,7 +49,7 @@ void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int count_per
|
||||
|
||||
void poweron_cp0(struct cp0* cp0)
|
||||
{
|
||||
uint32_t* cp0_regs;
|
||||
uint64_t* cp0_regs;
|
||||
unsigned int* cp0_next_interrupt;
|
||||
int* cp0_cycle_count;
|
||||
|
||||
@@ -65,7 +65,7 @@ void poweron_cp0(struct cp0* cp0)
|
||||
cp0_regs[CP0_COUNT_REG] = UINT32_C(0x5000);
|
||||
cp0_regs[CP0_CAUSE_REG] = UINT32_C(0x5c);
|
||||
cp0_regs[CP0_CONTEXT_REG] = UINT32_C(0x7ffff0);
|
||||
cp0_regs[CP0_EPC_REG] = UINT32_C(0xffffffff);
|
||||
cp0_regs[CP0_EPC_REG] = UINT64_C(0xffffffffffffffff);
|
||||
cp0_regs[CP0_BADVADDR_REG] = UINT32_C(0xffffffff);
|
||||
cp0_regs[CP0_ERROREPC_REG] = UINT32_C(0xffffffff);
|
||||
|
||||
@@ -81,7 +81,7 @@ void poweron_cp0(struct cp0* cp0)
|
||||
}
|
||||
|
||||
|
||||
uint32_t* r4300_cp0_regs(struct cp0* cp0)
|
||||
uint64_t* r4300_cp0_regs(struct cp0* cp0)
|
||||
{
|
||||
#ifndef NEW_DYNAREC
|
||||
return cp0->regs;
|
||||
@@ -124,7 +124,7 @@ int* r4300_cp0_cycle_count(struct cp0* cp0)
|
||||
|
||||
int check_cop1_unusable(struct r4300_core* r4300)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
if (!(cp0_regs[CP0_STATUS_REG] & CP0_STATUS_CU1))
|
||||
{
|
||||
@@ -137,7 +137,7 @@ int check_cop1_unusable(struct r4300_core* r4300)
|
||||
|
||||
int check_cop2_unusable(struct r4300_core* r4300)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
if (!(cp0_regs[CP0_STATUS_REG] & CP0_STATUS_CU2))
|
||||
{
|
||||
@@ -151,7 +151,7 @@ int check_cop2_unusable(struct r4300_core* r4300)
|
||||
void cp0_update_count(struct r4300_core* r4300)
|
||||
{
|
||||
struct cp0* cp0 = &r4300->cp0;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
|
||||
#ifdef NEW_DYNAREC
|
||||
if (r4300->emumode != EMUMODE_DYNAREC)
|
||||
@@ -213,7 +213,7 @@ static void exception_epilog(struct r4300_core* r4300)
|
||||
|
||||
void TLB_refill_exception(struct r4300_core* r4300, uint32_t address, int w)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
int usual_handler = 0, i;
|
||||
|
||||
if (r4300->emumode != EMUMODE_DYNAREC && w != 2) {
|
||||
@@ -246,8 +246,8 @@ void TLB_refill_exception(struct r4300_core* r4300, uint32_t address, int w)
|
||||
if (r4300->emumode != EMUMODE_PURE_INTERPRETER)
|
||||
{
|
||||
cp0_regs[CP0_EPC_REG] = (w != 2)
|
||||
? *r4300_pc(r4300)
|
||||
: address;
|
||||
? SE32(*r4300_pc(r4300))
|
||||
: SE32(address);
|
||||
}
|
||||
else {
|
||||
cp0_regs[CP0_EPC_REG] = *r4300_pc(r4300);
|
||||
@@ -297,12 +297,12 @@ void TLB_refill_exception(struct r4300_core* r4300, uint32_t address, int w)
|
||||
|
||||
void exception_general(struct r4300_core* r4300)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
cp0_update_count(r4300);
|
||||
cp0_regs[CP0_STATUS_REG] |= CP0_STATUS_EXL;
|
||||
|
||||
cp0_regs[CP0_EPC_REG] = *r4300_pc(r4300);
|
||||
cp0_regs[CP0_EPC_REG] = SE32(*r4300_pc(r4300));
|
||||
|
||||
if (r4300->delay_slot == 1 || r4300->delay_slot == 3)
|
||||
{
|
||||
|
||||
+2
-2
@@ -184,7 +184,7 @@ struct cp0
|
||||
{
|
||||
#ifndef NEW_DYNAREC
|
||||
/* New dynarec uses a different memory layout */
|
||||
uint32_t regs[CP0_REGS_COUNT];
|
||||
uint64_t regs[CP0_REGS_COUNT];
|
||||
uint64_t latch;
|
||||
#endif
|
||||
|
||||
@@ -227,7 +227,7 @@ struct cp0
|
||||
void init_cp0(struct cp0* cp0, unsigned int count_per_op, unsigned int count_per_op_denom_pot, struct new_dynarec_hot_state* new_dynarec_hot_state, const struct interrupt_handler* interrupt_handlers);
|
||||
void poweron_cp0(struct cp0* cp0);
|
||||
|
||||
uint32_t* r4300_cp0_regs(struct cp0* cp0);
|
||||
uint64_t* r4300_cp0_regs(struct cp0* cp0);
|
||||
uint64_t* r4300_cp0_latch(struct cp0* cp0);
|
||||
uint32_t* r4300_cp0_last_addr(struct cp0* cp0);
|
||||
unsigned int* r4300_cp0_next_interrupt(struct cp0* cp0);
|
||||
|
||||
+12
-12
@@ -100,7 +100,7 @@ static void clear_queue(struct interrupt_queue* q)
|
||||
|
||||
static int before_event(const struct cp0* cp0, unsigned int evt1, unsigned int evt2, int type2)
|
||||
{
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs((struct cp0*)cp0); /* OK to cast away const qualifier */
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs((struct cp0*)cp0); /* OK to cast away const qualifier */
|
||||
uint32_t count = cp0_regs[CP0_COUNT_REG];
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count((struct cp0*)cp0);
|
||||
|
||||
@@ -128,7 +128,7 @@ unsigned int add_random_interrupt_time(struct r4300_core* r4300)
|
||||
|
||||
void add_interrupt_event(struct cp0* cp0, int type, unsigned int delay)
|
||||
{
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
add_interrupt_event_count(cp0, type, cp0_regs[CP0_COUNT_REG] + delay);
|
||||
}
|
||||
|
||||
@@ -136,7 +136,7 @@ void add_interrupt_event_count(struct cp0* cp0, int type, unsigned int count)
|
||||
{
|
||||
struct node* event;
|
||||
struct node* e;
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
unsigned int* cp0_next_interrupt = r4300_cp0_next_interrupt(cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(cp0);
|
||||
|
||||
@@ -191,7 +191,7 @@ void add_interrupt_event_count(struct cp0* cp0, int type, unsigned int count)
|
||||
void remove_interrupt_event(struct cp0* cp0)
|
||||
{
|
||||
struct node* e;
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
unsigned int* cp0_next_interrupt = r4300_cp0_next_interrupt(cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(cp0);
|
||||
|
||||
@@ -264,7 +264,7 @@ void remove_event(struct interrupt_queue* q, int type)
|
||||
void translate_event_queue(struct cp0* cp0, unsigned int base)
|
||||
{
|
||||
struct node* e;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(cp0);
|
||||
|
||||
remove_event(&cp0->q, COMPARE_INT);
|
||||
@@ -309,7 +309,7 @@ int save_eventqueue_infos(const struct cp0* cp0, char *buf)
|
||||
void load_eventqueue_infos(struct cp0* cp0, const char *buf)
|
||||
{
|
||||
int len = 0;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
|
||||
clear_queue(&cp0->q);
|
||||
|
||||
@@ -335,7 +335,7 @@ void init_interrupt(struct cp0* cp0)
|
||||
void r4300_check_interrupt(struct r4300_core* r4300, uint32_t cause_ip, int set_cause)
|
||||
{
|
||||
struct node* event;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
unsigned int* cp0_next_interrupt = r4300_cp0_next_interrupt(&r4300->cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0);
|
||||
|
||||
@@ -379,7 +379,7 @@ void r4300_check_interrupt(struct r4300_core* r4300, uint32_t cause_ip, int set_
|
||||
|
||||
void raise_maskable_interrupt(struct r4300_core* r4300, uint32_t cause_ip)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CAUSE_REG] = (cp0_regs[CP0_CAUSE_REG] | cause_ip) & ~CP0_CAUSE_EXCCODE_MASK;
|
||||
|
||||
if (!(cp0_regs[CP0_STATUS_REG] & cp0_regs[CP0_CAUSE_REG] & UINT32_C(0xff00))) {
|
||||
@@ -396,7 +396,7 @@ void raise_maskable_interrupt(struct r4300_core* r4300, uint32_t cause_ip)
|
||||
void compare_int_handler(void* opaque)
|
||||
{
|
||||
struct r4300_core* r4300 = (struct r4300_core*)opaque;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0);
|
||||
|
||||
/* Add count_per_op to avoid wrong event order in case CP0_COUNT_REG == CP0_COMPARE_REG */
|
||||
@@ -422,7 +422,7 @@ void check_int_handler(void* opaque)
|
||||
void special_int_handler(void* opaque)
|
||||
{
|
||||
struct cp0* cp0 = (struct cp0*)opaque;
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
|
||||
remove_interrupt_event(cp0);
|
||||
add_interrupt_event_count(cp0, SPECIAL_INT, ((cp0_regs[CP0_COUNT_REG] & UINT32_C(0x80000000)) ^ UINT32_C(0x80000000)));
|
||||
@@ -434,7 +434,7 @@ void nmi_int_handler(void* opaque)
|
||||
{
|
||||
struct device* dev = (struct device*)opaque;
|
||||
struct r4300_core* r4300 = &dev->r4300;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
reset_pif(&dev->pif, 1);
|
||||
|
||||
@@ -537,7 +537,7 @@ static void call_interrupt_handler(const struct cp0* cp0, size_t index)
|
||||
|
||||
void gen_interrupt(struct r4300_core* r4300)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
unsigned int* cp0_next_interrupt = r4300_cp0_next_interrupt(&r4300->cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0);
|
||||
|
||||
|
||||
@@ -115,7 +115,7 @@ DECLARE_INSTRUCTION(RESERVED)
|
||||
{
|
||||
DECLARE_R4300
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
DebugMessage(M64MSG_ERROR, "reserved opcode: %" PRIX32 ":%" PRIX32, PCADDR, *fast_mem_access(r4300, PCADDR));
|
||||
|
||||
@@ -127,7 +127,7 @@ DECLARE_INSTRUCTION(RESERVED_COP2)
|
||||
{
|
||||
DECLARE_R4300
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
if (check_cop2_unusable(r4300)) { return; }
|
||||
|
||||
@@ -140,7 +140,7 @@ DECLARE_INSTRUCTION(RESERVED_COP2)
|
||||
DECLARE_INSTRUCTION(BREAK)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_BP;
|
||||
exception_general(r4300);
|
||||
@@ -221,11 +221,23 @@ DECLARE_INSTRUCTION(LL)
|
||||
DECLARE_INSTRUCTION(LW)
|
||||
{
|
||||
DECLARE_R4300
|
||||
const uint32_t lsaddr = (uint32_t) irs32 + (uint32_t) iimmediate;
|
||||
const uint64_t lsaddr = (int64_t) irs + (int16_t) iimmediate;
|
||||
int64_t *lsrtp = &irt;
|
||||
ADD_TO_PC(1);
|
||||
uint32_t value;
|
||||
|
||||
if (lsaddr & 3) {
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
//
|
||||
cp0_regs[CP0_CONTEXT_REG] = (cp0_regs[CP0_CONTEXT_REG] & 0xffffffffff800000) | (lsaddr >> 9 & 0x00000000007FFFF0);
|
||||
cp0_regs[CP0_XCONTEXT_REG] = (cp0_regs[CP0_CONTEXT_REG] & 0xffffffffff800000) | (lsaddr >> 9 & 0x7FFFFFF0) | (lsaddr >> 31 & 0x80000000) | ((int64_t)1 << 32);
|
||||
cp0_regs[CP0_BADVADDR_REG] = lsaddr;
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_ADEL;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
|
||||
ADD_TO_PC(1);
|
||||
|
||||
if (r4300_read_aligned_word(r4300, lsaddr, &value)) {
|
||||
*lsrtp = SE32(value);
|
||||
}
|
||||
@@ -374,8 +386,19 @@ DECLARE_INSTRUCTION(SC)
|
||||
DECLARE_INSTRUCTION(SW)
|
||||
{
|
||||
DECLARE_R4300
|
||||
const uint32_t lsaddr = (uint32_t) irs32 + (uint32_t) iimmediate;
|
||||
const uint64_t lsaddr = (int64_t) irs + (int16_t) iimmediate;
|
||||
int64_t *lsrtp = &irt;
|
||||
|
||||
if (lsaddr & 3) {
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_regs[CP0_CONTEXT_REG] = (lsaddr >> 9 & 0x007FFFF0);
|
||||
cp0_regs[CP0_XCONTEXT_REG] = (lsaddr >> 9 & 0x7FFFFFF0) | (lsaddr >> 31 & 0x80000000) | ((int64_t)1 << 32);
|
||||
cp0_regs[CP0_BADVADDR_REG] = lsaddr;
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_ADES;
|
||||
exception_general(r4300);
|
||||
return;
|
||||
}
|
||||
|
||||
ADD_TO_PC(1);
|
||||
|
||||
r4300_write_aligned_word(r4300, lsaddr, (uint32_t)*lsrtp, ~UINT32_C(0));
|
||||
@@ -993,7 +1016,7 @@ DECLARE_INSTRUCTION(CACHE)
|
||||
DECLARE_INSTRUCTION(ERET)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0);
|
||||
|
||||
cp0_update_count(r4300);
|
||||
@@ -1022,7 +1045,7 @@ DECLARE_INSTRUCTION(SYNC)
|
||||
DECLARE_INSTRUCTION(SYSCALL)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_SYS;
|
||||
exception_general(r4300);
|
||||
@@ -1034,7 +1057,7 @@ DECLARE_INSTRUCTION(SYSCALL)
|
||||
DECLARE_INSTRUCTION(name) \
|
||||
{ \
|
||||
DECLARE_R4300 \
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
if (cond) \
|
||||
{ \
|
||||
cp0_regs[CP0_CAUSE_REG] = CP0_CAUSE_EXCCODE_TR; \
|
||||
@@ -1067,7 +1090,7 @@ DECLARE_INSTRUCTION(TLBP)
|
||||
{
|
||||
DECLARE_R4300
|
||||
int i;
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
cp0_regs[CP0_INDEX_REG] |= UINT32_C(0x80000000);
|
||||
for (i = 0; i < 32; ++i)
|
||||
@@ -1087,7 +1110,7 @@ DECLARE_INSTRUCTION(TLBP)
|
||||
DECLARE_INSTRUCTION(TLBR)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
int index;
|
||||
index = cp0_regs[CP0_INDEX_REG] & UINT32_C(0x1F);
|
||||
@@ -1104,7 +1127,7 @@ DECLARE_INSTRUCTION(TLBR)
|
||||
|
||||
static void TLBWrite(struct r4300_core* r4300, unsigned int idx)
|
||||
{
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint32_t pc_addr = *r4300_pc(r4300);
|
||||
|
||||
if (pc_addr >= r4300->cp0.tlb.entries[idx].start_even && pc_addr < r4300->cp0.tlb.entries[idx].end_even && r4300->cp0.tlb.entries[idx].v_even)
|
||||
@@ -1218,7 +1241,7 @@ static void TLBWrite(struct r4300_core* r4300, unsigned int idx)
|
||||
DECLARE_INSTRUCTION(TLBWR)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
cp0_update_count(r4300);
|
||||
cp0_regs[CP0_RANDOM_REG] = (cp0_regs[CP0_COUNT_REG]/r4300->cp0.count_per_op % (32 - cp0_regs[CP0_WIRED_REG]))
|
||||
+ cp0_regs[CP0_WIRED_REG];
|
||||
@@ -1229,31 +1252,32 @@ DECLARE_INSTRUCTION(TLBWR)
|
||||
DECLARE_INSTRUCTION(TLBWI)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
TLBWrite(r4300, cp0_regs[CP0_INDEX_REG] & UINT32_C(0x3F));
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
/* CP0 load/store instructions */
|
||||
#include <stdio.h>
|
||||
|
||||
DECLARE_INSTRUCTION(MFC0)
|
||||
static osal_inline uint64_t get_cp0_register(struct r4300_core* r4300, uint8_t reg)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_latch = r4300_cp0_latch(&r4300->cp0);
|
||||
|
||||
switch(rfs)
|
||||
uint64_t data;
|
||||
switch (reg)
|
||||
{
|
||||
case CP0_RANDOM_REG:
|
||||
cp0_update_count(r4300);
|
||||
cp0_regs[CP0_RANDOM_REG] = (cp0_regs[CP0_COUNT_REG]/r4300->cp0.count_per_op % (32 - cp0_regs[CP0_WIRED_REG]))
|
||||
+ cp0_regs[CP0_WIRED_REG];
|
||||
rrt = SE32(cp0_regs[rfs]);
|
||||
data = cp0_regs[reg];
|
||||
break;
|
||||
case CP0_COUNT_REG:
|
||||
cp0_update_count(r4300);
|
||||
rrt = SE32(cp0_regs[rfs]);
|
||||
data = cp0_regs[reg];
|
||||
break;
|
||||
case CP0_UNUSED_7:
|
||||
case CP0_UNUSED_21:
|
||||
@@ -1262,90 +1286,53 @@ DECLARE_INSTRUCTION(MFC0)
|
||||
case CP0_UNUSED_24:
|
||||
case CP0_UNUSED_25:
|
||||
case CP0_UNUSED_31:
|
||||
rrt = (*cp0_latch);
|
||||
data = (*cp0_latch);
|
||||
break;
|
||||
default:
|
||||
rrt = SE32(cp0_regs[rfs]);
|
||||
data = cp0_regs[reg];
|
||||
break;
|
||||
}
|
||||
|
||||
ADD_TO_PC(1);
|
||||
return data;
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(DMFC0)
|
||||
static osal_inline void set_cp0_register(struct r4300_core* r4300, uint8_t reg, uint64_t value)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_latch = r4300_cp0_latch(&r4300->cp0);
|
||||
|
||||
switch(rfs)
|
||||
{
|
||||
case CP0_RANDOM_REG:
|
||||
cp0_update_count(r4300);
|
||||
cp0_regs[CP0_RANDOM_REG] = (cp0_regs[CP0_COUNT_REG]/r4300->cp0.count_per_op % (32 - cp0_regs[CP0_WIRED_REG]))
|
||||
+ cp0_regs[CP0_WIRED_REG];
|
||||
rrt = cp0_regs[rfs];
|
||||
break;
|
||||
case CP0_COUNT_REG:
|
||||
cp0_update_count(r4300);
|
||||
rrt = cp0_regs[rfs];
|
||||
break;
|
||||
case CP0_EPC_REG:
|
||||
rrt = SE32(cp0_regs[rfs]);
|
||||
break;
|
||||
case CP0_UNUSED_7:
|
||||
case CP0_UNUSED_21:
|
||||
case CP0_UNUSED_22:
|
||||
case CP0_UNUSED_23:
|
||||
case CP0_UNUSED_24:
|
||||
case CP0_UNUSED_25:
|
||||
case CP0_UNUSED_31:
|
||||
rrt = (*cp0_latch);
|
||||
break;
|
||||
default:
|
||||
rrt = cp0_regs[rfs];
|
||||
break;
|
||||
}
|
||||
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(MTC0)
|
||||
{
|
||||
DECLARE_R4300
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_latch = r4300_cp0_latch(&r4300->cp0);
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0);
|
||||
|
||||
(*cp0_latch) = rrt32;
|
||||
(*cp0_latch) = value;
|
||||
|
||||
switch(rfs)
|
||||
switch (reg)
|
||||
{
|
||||
case CP0_INDEX_REG:
|
||||
cp0_regs[CP0_INDEX_REG] = rrt32 & UINT32_C(0x8000003F);
|
||||
cp0_regs[CP0_INDEX_REG] = value & UINT32_C(0x8000003F);
|
||||
if ((cp0_regs[CP0_INDEX_REG] & UINT32_C(0x3F)) > UINT32_C(31))
|
||||
{
|
||||
DebugMessage(M64MSG_ERROR, "MTC0 instruction writing Index register with TLB index > 31");
|
||||
*r4300_stop(r4300)=1;
|
||||
//DebugMessage(M64MSG_ERROR, "MTC0 instruction writing Index register with TLB index > 31");
|
||||
//*r4300_stop(r4300)=1;
|
||||
}
|
||||
break;
|
||||
case CP0_RANDOM_REG:
|
||||
break;
|
||||
case CP0_ENTRYLO0_REG:
|
||||
cp0_regs[CP0_ENTRYLO0_REG] = rrt32 & UINT32_C(0x3FFFFFFF);
|
||||
cp0_regs[CP0_ENTRYLO0_REG] = value & UINT32_C(0x3FFFFFFF);
|
||||
break;
|
||||
case CP0_ENTRYLO1_REG:
|
||||
cp0_regs[CP0_ENTRYLO1_REG] = rrt32 & UINT32_C(0x3FFFFFFF);
|
||||
cp0_regs[CP0_ENTRYLO1_REG] = value & UINT32_C(0x3FFFFFFF);
|
||||
break;
|
||||
case CP0_CONTEXT_REG:
|
||||
cp0_regs[CP0_CONTEXT_REG] = (rrt32 & UINT32_C(0xFF800000))
|
||||
| (cp0_regs[CP0_CONTEXT_REG] & UINT32_C(0x007FFFF0));
|
||||
// 0xffffffffff800000
|
||||
cp0_regs[CP0_CONTEXT_REG] = value & UINT64_C(0xffffffffff800000);
|
||||
break;
|
||||
case CP0_XCONTEXT_REG:
|
||||
//cp0_regs[CP0_XCONTEXT_REG] = value & UINT64_C(0xffffffffff800000);
|
||||
break;
|
||||
case CP0_PAGEMASK_REG:
|
||||
cp0_regs[CP0_PAGEMASK_REG] = rrt32 & UINT32_C(0x01FFE000);
|
||||
cp0_regs[CP0_PAGEMASK_REG] = value & UINT32_C(0x01FFE000);
|
||||
break;
|
||||
case CP0_WIRED_REG:
|
||||
cp0_regs[CP0_WIRED_REG] = rrt32 & UINT32_C(0x0000003F);
|
||||
cp0_regs[CP0_WIRED_REG] = value & UINT32_C(0x0000003F);
|
||||
cp0_regs[CP0_RANDOM_REG] = UINT32_C(31);
|
||||
break;
|
||||
case CP0_BADVADDR_REG:
|
||||
@@ -1355,10 +1342,10 @@ DECLARE_INSTRUCTION(MTC0)
|
||||
r4300->cp0.interrupt_unsafe_state |= INTR_UNSAFE_R4300;
|
||||
if (*cp0_cycle_count >= 0) { gen_interrupt(r4300); }
|
||||
r4300->cp0.interrupt_unsafe_state &= ~INTR_UNSAFE_R4300;
|
||||
translate_event_queue(&r4300->cp0, rrt32);
|
||||
translate_event_queue(&r4300->cp0, value);
|
||||
break;
|
||||
case CP0_ENTRYHI_REG:
|
||||
cp0_regs[CP0_ENTRYHI_REG] = rrt32 & UINT32_C(0xFFFFE0FF);
|
||||
cp0_regs[CP0_ENTRYHI_REG] = value & UINT32_C(0xFFFFE0FF);
|
||||
break;
|
||||
case CP0_COMPARE_REG:
|
||||
cp0_update_count(r4300);
|
||||
@@ -1367,21 +1354,21 @@ DECLARE_INSTRUCTION(MTC0)
|
||||
/* Add count_per_op to avoid wrong event order in case CP0_COUNT_REG == CP0_COMPARE_REG */
|
||||
cp0_regs[CP0_COUNT_REG] += r4300->cp0.count_per_op;
|
||||
*cp0_cycle_count += r4300->cp0.count_per_op;
|
||||
add_interrupt_event_count(&r4300->cp0, COMPARE_INT, rrt32);
|
||||
add_interrupt_event_count(&r4300->cp0, COMPARE_INT, value);
|
||||
cp0_regs[CP0_COUNT_REG] -= r4300->cp0.count_per_op;
|
||||
|
||||
/* Update next interrupt in case first event is COMPARE_INT */
|
||||
*cp0_cycle_count = cp0_regs[CP0_COUNT_REG] - r4300->cp0.q.first->data.count;
|
||||
cp0_regs[CP0_COMPARE_REG] = rrt32;
|
||||
cp0_regs[CP0_COMPARE_REG] = value;
|
||||
cp0_regs[CP0_CAUSE_REG] &= ~CP0_CAUSE_IP7;
|
||||
break;
|
||||
case CP0_STATUS_REG:
|
||||
rrt32 &= ~UINT32_C(0x080000); /* 19th bit isn't writable */
|
||||
value &= ~UINT32_C(0x080000); /* 19th bit isn't writable */
|
||||
|
||||
if((rrt32 & CP0_STATUS_FR) != (cp0_regs[CP0_STATUS_REG] & CP0_STATUS_FR))
|
||||
set_fpr_pointers(&r4300->cp1, rrt32);
|
||||
if((value & CP0_STATUS_FR) != (cp0_regs[CP0_STATUS_REG] & CP0_STATUS_FR))
|
||||
set_fpr_pointers(&r4300->cp1, value);
|
||||
|
||||
cp0_regs[CP0_STATUS_REG] = rrt32;
|
||||
cp0_regs[CP0_STATUS_REG] = value;
|
||||
ADD_TO_PC(1);
|
||||
cp0_update_count(r4300);
|
||||
r4300_check_interrupt(r4300, CP0_CAUSE_IP2, r4300->mi->regs[MI_INTR_REG] & r4300->mi->regs[MI_INTR_MASK_REG]); // ???
|
||||
@@ -1391,50 +1378,79 @@ DECLARE_INSTRUCTION(MTC0)
|
||||
return;
|
||||
case CP0_CAUSE_REG:
|
||||
cp0_regs[CP0_CAUSE_REG] &= ~(CP0_CAUSE_IP0 | CP0_CAUSE_IP1);
|
||||
cp0_regs[CP0_CAUSE_REG] |= rrt32 & (CP0_CAUSE_IP0 | CP0_CAUSE_IP1);
|
||||
cp0_regs[CP0_CAUSE_REG] |= value & (CP0_CAUSE_IP0 | CP0_CAUSE_IP1);
|
||||
break;
|
||||
case CP0_EPC_REG:
|
||||
cp0_regs[CP0_EPC_REG] = rrt32;
|
||||
cp0_regs[CP0_EPC_REG] = value;
|
||||
break;
|
||||
case CP0_PREVID_REG:
|
||||
break;
|
||||
case CP0_CONFIG_REG:
|
||||
cp0_regs[CP0_CONFIG_REG] = (rrt32 & UINT32_C(0x0000000F))
|
||||
cp0_regs[CP0_CONFIG_REG] = (value & UINT32_C(0x0000000F))
|
||||
| (cp0_regs[CP0_CONFIG_REG] & UINT32_C(0x00008000))
|
||||
| (cp0_regs[CP0_CONFIG_REG] & UINT32_C(0x7FFFFFFF));
|
||||
break;
|
||||
case CP0_LLADDR_REG:
|
||||
cp0_regs[CP0_LLADDR_REG] = rrt32;
|
||||
cp0_regs[CP0_LLADDR_REG] = value;
|
||||
break;
|
||||
case CP0_WATCHLO_REG:
|
||||
cp0_regs[CP0_WATCHLO_REG] = rrt32;
|
||||
cp0_regs[CP0_WATCHLO_REG] = value;
|
||||
break;
|
||||
case CP0_WATCHHI_REG:
|
||||
cp0_regs[CP0_WATCHHI_REG] = rrt32;
|
||||
break;
|
||||
case CP0_XCONTEXT_REG:
|
||||
cp0_regs[CP0_WATCHHI_REG] = value;
|
||||
break;
|
||||
case CP0_CACHEERR_REG:
|
||||
break;
|
||||
case CP0_PARITYERR_REG:
|
||||
cp0_regs[CP0_PARITYERR_REG] = rrt32 & UINT32_C(0x000000FF);
|
||||
cp0_regs[CP0_PARITYERR_REG] = value & UINT32_C(0x000000FF);
|
||||
break;
|
||||
case CP0_TAGLO_REG:
|
||||
cp0_regs[CP0_TAGLO_REG] = rrt32 & UINT32_C(0x0FFFFFC0);
|
||||
cp0_regs[CP0_TAGLO_REG] = value & UINT32_C(0x0FFFFFC0);
|
||||
break;
|
||||
case CP0_TAGHI_REG:
|
||||
cp0_regs[CP0_TAGHI_REG] = 0;
|
||||
break;
|
||||
case CP0_ERROREPC_REG:
|
||||
cp0_regs[CP0_ERROREPC_REG] = rrt32;
|
||||
cp0_regs[CP0_ERROREPC_REG] = value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(MFC0)
|
||||
{
|
||||
DECLARE_R4300
|
||||
rrt32 = SE32(get_cp0_register(r4300, rfs));
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(DMFC0)
|
||||
{
|
||||
DECLARE_R4300
|
||||
rrt = get_cp0_register(r4300, rfs);
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(MTC0)
|
||||
{
|
||||
DECLARE_R4300
|
||||
set_cp0_register(r4300, rfs, rrt32);
|
||||
if (rfs == CP0_STATUS_REG)
|
||||
return;
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
DECLARE_INSTRUCTION(DMTC0)
|
||||
{
|
||||
DECLARE_R4300
|
||||
set_cp0_register(r4300, rfs, rrt);
|
||||
if (rfs == CP0_STATUS_REG)
|
||||
return;
|
||||
ADD_TO_PC(1);
|
||||
}
|
||||
|
||||
|
||||
/* CP1 load/store instructions */
|
||||
|
||||
DECLARE_INSTRUCTION(LWC1)
|
||||
@@ -1517,7 +1533,7 @@ DECLARE_INSTRUCTION(DCFC1)
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
fpu_reset_cause(r4300_cp1_fcr31(&r4300->cp1));
|
||||
|
||||
@@ -1563,7 +1579,7 @@ DECLARE_INSTRUCTION(DCTC1)
|
||||
DECLARE_R4300
|
||||
if (check_cop1_unusable(r4300)) { return; }
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
|
||||
|
||||
fpu_reset_cause(r4300_cp1_fcr31(&r4300->cp1));
|
||||
|
||||
|
||||
+1
-1
@@ -66,7 +66,7 @@ struct new_dynarec_hot_state
|
||||
int64_t regs[32];
|
||||
int64_t hi;
|
||||
int64_t lo;
|
||||
uint32_t cp0_regs[32];
|
||||
uint64_t cp0_regs[32];
|
||||
uint64_t cp0_latch;
|
||||
float* cp1_regs_simple[32];
|
||||
double* cp1_regs_double[32];
|
||||
|
||||
@@ -76,7 +76,7 @@ static void InterpretOpcode(struct r4300_core* r4300);
|
||||
} \
|
||||
static void name##_IDLE(struct r4300_core* r4300, uint32_t op) \
|
||||
{ \
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&r4300->cp0); \
|
||||
int* cp0_cycle_count = r4300_cp0_cycle_count(&r4300->cp0); \
|
||||
const int take_jump = (condition); \
|
||||
if (cop1 && check_cop1_unusable(r4300)) return; \
|
||||
@@ -443,9 +443,11 @@ void InterpretOpcode(struct r4300_core* r4300)
|
||||
else NOP(r4300, 0);
|
||||
break;
|
||||
case 4: /* Coprocessor 0 opcode 4: MTC0 */
|
||||
case 5: /* Coprocessor 0 opcode 5: DMTC0 */
|
||||
MTC0(r4300, op);
|
||||
break;
|
||||
case 5: /* Coprocessor 0 opcode 5: DMTC0 */
|
||||
DMTC0(r4300, op);
|
||||
break;
|
||||
case 16: /* Coprocessor 0 opcode 16: TLB */
|
||||
switch (op & 0x3F) {
|
||||
case 1: TLBR(r4300, op); break;
|
||||
@@ -686,8 +688,7 @@ void InterpretOpcode(struct r4300_core* r4300)
|
||||
else NOP(r4300, 0);
|
||||
break;
|
||||
case 35: /* Major opcode 35: LW */
|
||||
if (RT_OF(op) != 0) LW(r4300, op);
|
||||
else NOP(r4300, 0);
|
||||
LW(r4300, op);
|
||||
break;
|
||||
case 36: /* Major opcode 36: LBU */
|
||||
if (RT_OF(op) != 0) LBU(r4300, op);
|
||||
|
||||
@@ -40,7 +40,7 @@ static uint32_t get_remaining_dma_length(struct ai_controller* ai)
|
||||
{
|
||||
unsigned int* next_ai_event;
|
||||
unsigned int remaining_dma_duration;
|
||||
const uint32_t* cp0_regs;
|
||||
const uint64_t* cp0_regs;
|
||||
|
||||
if (ai->fifo[0].duration == 0)
|
||||
return 0;
|
||||
|
||||
@@ -87,7 +87,7 @@ void read_vi_regs(void* opaque, uint32_t address, uint32_t* value)
|
||||
{
|
||||
struct vi_controller* vi = (struct vi_controller*)opaque;
|
||||
uint32_t reg = vi_reg(address);
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(&vi->mi->r4300->cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(&vi->mi->r4300->cp0);
|
||||
|
||||
if (reg == VI_CURRENT_REG)
|
||||
{
|
||||
|
||||
@@ -1071,6 +1071,7 @@ static void pause_loop(void)
|
||||
* Allow the core to perform various things */
|
||||
void new_vi(void)
|
||||
{
|
||||
new_frame();
|
||||
#if defined(PROFILE)
|
||||
timed_sections_refresh();
|
||||
#endif
|
||||
|
||||
+1
-1
@@ -818,7 +818,7 @@ void netplay_check_sync(struct cp0* cp0)
|
||||
|
||||
if (l_vi_counter % 600 == 0)
|
||||
{
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs(cp0);
|
||||
|
||||
l_check_sync_packet->data[0] = UDP_SYNC_DATA;
|
||||
netplay_write32(l_vi_counter, &l_check_sync_packet->data[1]); //current VI count
|
||||
|
||||
+18
-11
@@ -63,7 +63,7 @@ enum { GB_CART_FINGERPRINT_OFFSET = 0x134 };
|
||||
enum { DD_DISK_ID_OFFSET = 0x43670 };
|
||||
|
||||
static const char* savestate_magic = "M64+SAVE";
|
||||
static const int savestate_latest_version = 0x00010900; /* 1.9 */
|
||||
static const int savestate_latest_version = 0x00020000; /* 2.0 */
|
||||
static const unsigned char pj64_magic[4] = { 0xC8, 0xA6, 0xD8, 0x23 };
|
||||
|
||||
static savestates_job job = savestates_job_nothing;
|
||||
@@ -208,7 +208,7 @@ static int savestates_load_m64p(struct device* dev, char *filepath)
|
||||
unsigned char using_tlb_data[4];
|
||||
unsigned char data_0001_0200[4096]; // 4k for extra state from v1.2
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
|
||||
|
||||
SDL_LockMutex(savestates_lock);
|
||||
|
||||
@@ -887,6 +887,14 @@ static int savestates_load_m64p(struct device* dev, char *filepath)
|
||||
*r4300_cp0_latch(&dev->r4300.cp0) = GETDATA(curr, uint64_t);
|
||||
*r4300_cp2_latch(&dev->r4300.cp2) = GETDATA(curr, uint64_t);
|
||||
}
|
||||
|
||||
if (version >= 0x00020000)
|
||||
{
|
||||
/* extra rsp state */
|
||||
dev->sp.rsp_status = GETDATA(curr, uint32_t);
|
||||
dev->sp.first_run = GETDATA(curr, uint32_t);
|
||||
dev->sp.rsp_wait = GETDATA(curr, uint32_t);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -958,9 +966,6 @@ static int savestates_load_m64p(struct device* dev, char *filepath)
|
||||
/* reset fb state */
|
||||
poweron_fb(&dev->dp.fb);
|
||||
|
||||
dev->sp.rsp_status = 0;
|
||||
dev->sp.rsp_wait = 0;
|
||||
dev->sp.first_run = 1;
|
||||
dev->r4300.cp0.interrupt_unsafe_state = 0;
|
||||
|
||||
*r4300_cp0_last_addr(&dev->r4300.cp0) = *r4300_pc(&dev->r4300);
|
||||
@@ -985,7 +990,7 @@ static int savestates_load_pj64(struct device* dev,
|
||||
size_t savestateSize;
|
||||
unsigned char *savestateData, *curr;
|
||||
|
||||
uint32_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
|
||||
uint64_t* cp0_regs = r4300_cp0_regs(&dev->r4300.cp0);
|
||||
|
||||
/* Read and check Project64 magic number. */
|
||||
if (!read_func(handle, header, 8))
|
||||
@@ -1264,9 +1269,6 @@ static int savestates_load_pj64(struct device* dev,
|
||||
// No flashram info in pj64 savestate.
|
||||
poweron_flashram(&dev->cart.flashram);
|
||||
|
||||
dev->sp.rsp_status = 0;
|
||||
dev->sp.rsp_wait = 0;
|
||||
dev->sp.first_run = 1;
|
||||
dev->r4300.cp0.interrupt_unsafe_state = 0;
|
||||
|
||||
/* extra fb state */
|
||||
@@ -1541,7 +1543,7 @@ static int savestates_save_m64p(const struct device* dev, char *filepath)
|
||||
char *curr;
|
||||
|
||||
/* OK to cast away const qualifier */
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
|
||||
|
||||
save = malloc(sizeof(*save));
|
||||
if (!save) {
|
||||
@@ -1928,6 +1930,11 @@ static int savestates_save_m64p(const struct device* dev, char *filepath)
|
||||
PUTDATA(curr, uint64_t, *r4300_cp0_latch((struct cp0*)&dev->r4300.cp0));
|
||||
PUTDATA(curr, uint64_t, *r4300_cp2_latch((struct cp2*)&dev->r4300.cp2));
|
||||
|
||||
/* rsp state (since 2.0) */
|
||||
PUTDATA(curr, uint32_t, dev->sp.rsp_status);
|
||||
PUTDATA(curr, uint32_t, dev->sp.first_run);
|
||||
PUTDATA(curr, uint32_t, dev->sp.rsp_wait);
|
||||
|
||||
init_work(&save->work, savestates_save_m64p_work);
|
||||
queue_work(&save->work);
|
||||
|
||||
@@ -1944,7 +1951,7 @@ static int savestates_save_pj64(const struct device* dev,
|
||||
size_t savestateSize;
|
||||
unsigned char *savestateData, *curr;
|
||||
|
||||
const uint32_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
|
||||
const uint64_t* cp0_regs = r4300_cp0_regs((struct cp0*)&dev->r4300.cp0);
|
||||
|
||||
// Allocate memory for the save state data
|
||||
savestateSize = 8 + SaveRDRAMSize + 0x2754;
|
||||
|
||||
+1
-1
@@ -71,7 +71,7 @@ impl GcAdapter {
|
||||
})
|
||||
.ok_or(rusb::Error::NoDevice)?;
|
||||
|
||||
let mut handle = device.open()?;
|
||||
let handle = device.open()?;
|
||||
|
||||
if handle.kernel_driver_active(0).unwrap_or(false) {
|
||||
handle.detach_kernel_driver(0)?;
|
||||
|
||||
+8
-12
@@ -359,25 +359,21 @@ impl BUTTONS__bindgen_ty_1 {
|
||||
}
|
||||
#[inline]
|
||||
pub fn X_AXIS(&self) -> ::std::os::raw::c_int {
|
||||
unsafe { ::std::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
|
||||
u32::cast_signed(self._bitfield_1.get(16usize, 8u8) as u32)
|
||||
}
|
||||
#[inline]
|
||||
pub fn set_X_AXIS(&mut self, val: ::std::os::raw::c_int) {
|
||||
unsafe {
|
||||
let val: u32 = ::std::mem::transmute(val);
|
||||
self._bitfield_1.set(16usize, 8u8, val as u64)
|
||||
}
|
||||
let val: u32 = i32::cast_unsigned(val);
|
||||
self._bitfield_1.set(16usize, 8u8, val as u64)
|
||||
}
|
||||
#[inline]
|
||||
pub fn Y_AXIS(&self) -> ::std::os::raw::c_int {
|
||||
unsafe { ::std::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
|
||||
u32::cast_signed(self._bitfield_1.get(24usize, 8u8) as u32)
|
||||
}
|
||||
#[inline]
|
||||
pub fn set_Y_AXIS(&mut self, val: ::std::os::raw::c_int) {
|
||||
unsafe {
|
||||
let val: u32 = ::std::mem::transmute(val);
|
||||
self._bitfield_1.set(24usize, 8u8, val as u64)
|
||||
}
|
||||
let val: u32 = i32::cast_unsigned(val);
|
||||
self._bitfield_1.set(24usize, 8u8, val as u64)
|
||||
}
|
||||
#[inline]
|
||||
pub fn new_bitfield_1(
|
||||
@@ -466,11 +462,11 @@ impl BUTTONS__bindgen_ty_1 {
|
||||
Reserved2 as u64
|
||||
});
|
||||
__bindgen_bitfield_unit.set(16usize, 8u8, {
|
||||
let X_AXIS: u32 = unsafe { ::std::mem::transmute(X_AXIS) };
|
||||
let X_AXIS: u32 = i32::cast_unsigned(X_AXIS);
|
||||
X_AXIS as u64
|
||||
});
|
||||
__bindgen_bitfield_unit.set(24usize, 8u8, {
|
||||
let Y_AXIS: u32 = unsafe { ::std::mem::transmute(Y_AXIS) };
|
||||
let Y_AXIS: u32 = i32::cast_unsigned(Y_AXIS);
|
||||
Y_AXIS as u64
|
||||
});
|
||||
__bindgen_bitfield_unit
|
||||
|
||||
+8
-12
@@ -359,25 +359,21 @@ impl BUTTONS__bindgen_ty_1 {
|
||||
}
|
||||
#[inline]
|
||||
pub fn X_AXIS(&self) -> ::std::os::raw::c_int {
|
||||
unsafe { ::std::mem::transmute(self._bitfield_1.get(16usize, 8u8) as u32) }
|
||||
u32::cast_signed(self._bitfield_1.get(16usize, 8u8) as u32)
|
||||
}
|
||||
#[inline]
|
||||
pub fn set_X_AXIS(&mut self, val: ::std::os::raw::c_int) {
|
||||
unsafe {
|
||||
let val: u32 = ::std::mem::transmute(val);
|
||||
self._bitfield_1.set(16usize, 8u8, val as u64)
|
||||
}
|
||||
let val: u32 = i32::cast_unsigned(val);
|
||||
self._bitfield_1.set(16usize, 8u8, val as u64)
|
||||
}
|
||||
#[inline]
|
||||
pub fn Y_AXIS(&self) -> ::std::os::raw::c_int {
|
||||
unsafe { ::std::mem::transmute(self._bitfield_1.get(24usize, 8u8) as u32) }
|
||||
u32::cast_signed(self._bitfield_1.get(24usize, 8u8) as u32)
|
||||
}
|
||||
#[inline]
|
||||
pub fn set_Y_AXIS(&mut self, val: ::std::os::raw::c_int) {
|
||||
unsafe {
|
||||
let val: u32 = ::std::mem::transmute(val);
|
||||
self._bitfield_1.set(24usize, 8u8, val as u64)
|
||||
}
|
||||
let val: u32 = i32::cast_unsigned(val);
|
||||
self._bitfield_1.set(24usize, 8u8, val as u64)
|
||||
}
|
||||
#[inline]
|
||||
pub fn new_bitfield_1(
|
||||
@@ -466,11 +462,11 @@ impl BUTTONS__bindgen_ty_1 {
|
||||
Reserved2 as u64
|
||||
});
|
||||
__bindgen_bitfield_unit.set(16usize, 8u8, {
|
||||
let X_AXIS: u32 = unsafe { ::std::mem::transmute(X_AXIS) };
|
||||
let X_AXIS: u32 = i32::cast_unsigned(X_AXIS);
|
||||
X_AXIS as u64
|
||||
});
|
||||
__bindgen_bitfield_unit.set(24usize, 8u8, {
|
||||
let Y_AXIS: u32 = unsafe { ::std::mem::transmute(Y_AXIS) };
|
||||
let Y_AXIS: u32 = i32::cast_unsigned(Y_AXIS);
|
||||
Y_AXIS as u64
|
||||
});
|
||||
__bindgen_bitfield_unit
|
||||
|
||||
+9
-2
@@ -129,13 +129,20 @@ void hle_execute(struct hle_t* hle)
|
||||
|
||||
if (!match)
|
||||
{
|
||||
/* wrap around when needed */
|
||||
if (cached_ucodes->count >= CACHED_UCODES_MAX_SIZE)
|
||||
cached_ucodes->count = 0;
|
||||
|
||||
info = &cached_ucodes->infos[cached_ucodes->count];
|
||||
info->uc_start = uc_start;
|
||||
info->uc_dstart = uc_dstart;
|
||||
info->uc_dsize = uc_dsize;
|
||||
info->uc_pfunc = task_detection(hle);
|
||||
cached_ucodes->count++;
|
||||
assert(cached_ucodes->count <= CACHED_UCODES_MAX_SIZE);
|
||||
|
||||
/* ensure we stay within bounds */
|
||||
if (cached_ucodes->count < CACHED_UCODES_MAX_SIZE)
|
||||
cached_ucodes->count++;
|
||||
|
||||
assert(info->uc_pfunc != NULL);
|
||||
}
|
||||
|
||||
|
||||
@@ -117,6 +117,14 @@ SettingsDialog::SettingsDialog(QWidget *parent, QString file) : QDialog(parent)
|
||||
// connect hotkey settings to slot
|
||||
this->commonHotkeySettings(SettingsDialogAction::ConnectSignals);
|
||||
|
||||
// set icons for certain buttons
|
||||
this->clearJapaneseIPLRomPathButton->setText("");
|
||||
this->clearJapaneseIPLRomPathButton->setIcon(QIcon::fromTheme("delete-bin-line"));
|
||||
this->clearAmericanIPLRomPathButton->setText("");
|
||||
this->clearAmericanIPLRomPathButton->setIcon(QIcon::fromTheme("delete-bin-line"));
|
||||
this->clearDevelopmentIPLRomPathButton->setText("");
|
||||
this->clearDevelopmentIPLRomPathButton->setIcon(QIcon::fromTheme("delete-bin-line"));
|
||||
|
||||
#ifndef NETPLAY
|
||||
this->innerInterfaceTabWidget->setTabVisible((int)SettingsDialogTab::InterfaceNetplay, false);
|
||||
#endif // !NETPLAY
|
||||
@@ -1405,6 +1413,21 @@ void SettingsDialog::on_changeDevelopmentIPLRomPathButton_clicked(void)
|
||||
this->chooseFile(this->developmentIPLRomLineEdit, tr("Open Japanese Development 64DD IPL"), "IPL ROMs (*.n64)");
|
||||
}
|
||||
|
||||
void SettingsDialog::on_clearJapaneseIPLRomPathButton_clicked(void)
|
||||
{
|
||||
this->japaneseIPLRomLineEdit->clear();
|
||||
}
|
||||
|
||||
void SettingsDialog::on_clearAmericanIPLRomPathButton_clicked(void)
|
||||
{
|
||||
this->americanIPLRomLineEdit->clear();
|
||||
}
|
||||
|
||||
void SettingsDialog::on_clearDevelopmentIPLRomPathButton_clicked(void)
|
||||
{
|
||||
this->developmentIPLRomLineEdit->clear();
|
||||
}
|
||||
|
||||
void SettingsDialog::on_changeBackgroundColorButton_clicked(void)
|
||||
{
|
||||
this->chooseColor(this->changeBackgroundColorButton, &this->currentBackgroundColor);
|
||||
|
||||
@@ -149,6 +149,10 @@ class SettingsDialog : public QDialog, private Ui::SettingsDialog
|
||||
void on_changeAmericanIPLRomPathButton_clicked(void);
|
||||
void on_changeDevelopmentIPLRomPathButton_clicked(void);
|
||||
|
||||
void on_clearJapaneseIPLRomPathButton_clicked(void);
|
||||
void on_clearAmericanIPLRomPathButton_clicked(void);
|
||||
void on_clearDevelopmentIPLRomPathButton_clicked(void);
|
||||
|
||||
void on_changeBackgroundColorButton_clicked(void);
|
||||
void on_changeTextColorButton_clicked(void);
|
||||
|
||||
|
||||
@@ -3031,6 +3031,13 @@
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
<item>
|
||||
<widget class="QPushButton" name="clearJapaneseIPLRomPathButton">
|
||||
<property name="text">
|
||||
<string>Clear</string>
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
</layout>
|
||||
</widget>
|
||||
</item>
|
||||
@@ -3054,6 +3061,13 @@
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
<item>
|
||||
<widget class="QPushButton" name="clearAmericanIPLRomPathButton">
|
||||
<property name="text">
|
||||
<string>Clear</string>
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
</layout>
|
||||
</widget>
|
||||
</item>
|
||||
@@ -3077,6 +3091,13 @@
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
<item>
|
||||
<widget class="QPushButton" name="clearDevelopmentIPLRomPathButton">
|
||||
<property name="text">
|
||||
<string>Clear</string>
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
</layout>
|
||||
</widget>
|
||||
</item>
|
||||
|
||||
Reference in New Issue
Block a user