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Xtensa ISA got specification for 64-bit floating point registers and opcodes, see ISA, 4.3.11 "Floating point coprocessor option". Add 64-bit FP registers. Although 64-bit floating point is currently not supported by xtensa translator, these registers need to be reported to gdb with proper size, otherwise it wouldn't find other registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
Description
Original Xbox Emulator for Windows, macOS, and Linux (Active Development)
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GPL-2.0
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