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Peter Maydell
1a8ffd6172
In commitebd394948d("target/hppa: Fix FPE exceptions") when we added the code for setting up the registers correctly on trapping FP exceptions, we accidentally broke the handling of the flag bits for non-trapping exceptions. In update_fr0_op() we incorrectly zero out the flag bits and the C bit, so any fp operation would clear previously set flag bits. We also stopped setting the flag bits when the fp operation raises an exception and the trap is not enabled. Adjust the code so that we set the Flag bits for every exception that happened and where the trap is not enabled. (This is the correct behaviour for the case where an instruction triggers two exceptions, one of which traps and one of which does not; that can only happen for inexact + underflow or inexact + overflow.) Cc: qemu-stable@nongnu.org Fixes:ebd394948d("target/hppa: Fix FPE exceptions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Helge Deller <deller@gmx.de> Tested-by: Helge Deller <deller@gmx.de> Message-ID: <20251017085350.895681-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>