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tricore bugfixes and RR1, RR2, RRPW and RRR insn # gpg: Signature made Tue 27 Jan 2015 12:02:06 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20150127: target-tricore: Add instructions of RRR opcode format target-tricore: Add instructions of RRPW opcode format target-tricore: Add instructions of RR2 opcode format target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode target-tricore: split up suov32 into suov32_pos and suov32_neg target-tricore: Fix bugs found by coverity target-tricore: calculate av bits before saturation target-tricore: Several translator and cpu model fixes target-tricore: Add missing ULL suffix on 64 bit constant Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
Description
Original Xbox Emulator for Windows, macOS, and Linux (Active Development)
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GPL-2.0
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