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synced 2026-07-11 01:24:41 +02:00
hw/core/register: remove the calls to `register_finalize_block'
This function is now a no-op. The register array is parented to the device and get finalized when the device is. Drop all the calls to `register_finalize_block'. Drop the RegisterInfoArray reference when it is not used elsewhere in the device. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com> Message-ID: <20251017161809.235740-4-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
committed by
Philippe Mathieu-Daudé
parent
5c6367bc1c
commit
f423f7ebac
+16
-22
@@ -634,17 +634,17 @@ static void versal_crl_init(Object *obj)
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XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
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XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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int i;
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xvcb->reg_array =
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register_init_block32(DEVICE(obj), crl_regs_info,
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ARRAY_SIZE(crl_regs_info),
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s->regs_info, s->regs,
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&crl_ops,
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XLNX_VERSAL_CRL_ERR_DEBUG,
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CRL_R_MAX * 4);
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reg_array = register_init_block32(DEVICE(obj), crl_regs_info,
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ARRAY_SIZE(crl_regs_info),
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s->regs_info, s->regs,
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&crl_ops,
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XLNX_VERSAL_CRL_ERR_DEBUG,
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CRL_R_MAX * 4);
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xvcb->regs = s->regs;
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sysbus_init_mmio(sbd, &xvcb->reg_array->mem);
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sysbus_init_mmio(sbd, ®_array->mem);
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sysbus_init_irq(sbd, &s->irq);
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for (i = 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) {
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@@ -688,17 +688,18 @@ static void versal2_crl_init(Object *obj)
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XlnxVersal2CRL *s = XLNX_VERSAL2_CRL(obj);
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XlnxVersalCRLBase *xvcb = XLNX_VERSAL_CRL_BASE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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size_t i;
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xvcb->reg_array = register_init_block32(DEVICE(obj), versal2_crl_regs_info,
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ARRAY_SIZE(versal2_crl_regs_info),
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s->regs_info, s->regs,
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&crl_ops,
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XLNX_VERSAL_CRL_ERR_DEBUG,
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VERSAL2_CRL_R_MAX * 4);
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reg_array = register_init_block32(DEVICE(obj), versal2_crl_regs_info,
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ARRAY_SIZE(versal2_crl_regs_info),
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s->regs_info, s->regs,
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&crl_ops,
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XLNX_VERSAL_CRL_ERR_DEBUG,
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VERSAL2_CRL_R_MAX * 4);
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xvcb->regs = s->regs;
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sysbus_init_mmio(sbd, &xvcb->reg_array->mem);
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sysbus_init_mmio(sbd, ®_array->mem);
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for (i = 0; i < ARRAY_SIZE(s->cfg.rpu); ++i) {
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object_property_add_link(obj, "rpu[*]", TYPE_ARM_CPU,
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@@ -750,12 +751,6 @@ static void versal2_crl_init(Object *obj)
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}
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}
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static void crl_finalize(Object *obj)
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{
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XlnxVersalCRLBase *s = XLNX_VERSAL_CRL_BASE(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_versal_crl = {
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.name = TYPE_XLNX_VERSAL_CRL,
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.version_id = 1,
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@@ -804,7 +799,6 @@ static const TypeInfo crl_base_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxVersalCRLBase),
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.class_size = sizeof(XlnxVersalCRLBaseClass),
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.instance_finalize = crl_finalize,
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.abstract = true,
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};
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@@ -627,7 +627,6 @@ static void trng_finalize(Object *obj)
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{
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XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj);
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register_finalize_block(s->reg_array);
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g_rand_free(s->prng);
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s->prng = NULL;
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}
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@@ -190,24 +190,19 @@ static void xram_ctrl_init(Object *obj)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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s->reg_array =
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reg_array =
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register_init_block32(DEVICE(obj), xram_ctrl_regs_info,
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ARRAY_SIZE(xram_ctrl_regs_info),
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s->regs_info, s->regs,
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&xram_ctrl_ops,
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XLNX_XRAM_CTRL_ERR_DEBUG,
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XRAM_CTRL_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_mmio(sbd, ®_array->mem);
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sysbus_init_irq(sbd, &s->irq);
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}
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static void xram_ctrl_finalize(Object *obj)
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{
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XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_xram_ctrl = {
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.name = TYPE_XLNX_XRAM_CTRL,
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.version_id = 1,
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@@ -241,7 +236,6 @@ static const TypeInfo xram_ctrl_info = {
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.instance_size = sizeof(XlnxXramCtrl),
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.class_init = xram_ctrl_class_init,
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.instance_init = xram_ctrl_init,
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.instance_finalize = xram_ctrl_finalize,
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};
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static void xram_ctrl_register_types(void)
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@@ -179,16 +179,17 @@ static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
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static void zynqmp_apu_init(Object *obj)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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RegisterInfoArray *reg_array;
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int i;
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s->reg_array =
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reg_array =
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register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
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ARRAY_SIZE(zynqmp_apu_regs_info),
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s->regs_info, s->regs,
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&zynqmp_apu_ops,
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XILINX_ZYNQMP_APU_ERR_DEBUG,
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APU_R_MAX * 4);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), ®_array->mem);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
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for (i = 0; i < APU_MAX_CPU; ++i) {
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@@ -208,12 +209,6 @@ static void zynqmp_apu_init(Object *obj)
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qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
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}
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static void zynqmp_apu_finalize(Object *obj)
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{
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XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_zynqmp_apu = {
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.name = TYPE_XLNX_ZYNQMP_APU_CTRL,
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.version_id = 1,
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@@ -241,7 +236,6 @@ static const TypeInfo zynqmp_apu_info = {
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.instance_size = sizeof(XlnxZynqMPAPUCtrl),
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.class_init = zynqmp_apu_class_init,
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.instance_init = zynqmp_apu_init,
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.instance_finalize = zynqmp_apu_finalize,
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};
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static void zynqmp_apu_register_types(void)
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@@ -211,24 +211,19 @@ static void crf_init(Object *obj)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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s->reg_array =
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reg_array =
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register_init_block32(DEVICE(obj), crf_regs_info,
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ARRAY_SIZE(crf_regs_info),
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s->regs_info, s->regs,
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&crf_ops,
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XLNX_ZYNQMP_CRF_ERR_DEBUG,
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CRF_R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_mmio(sbd, ®_array->mem);
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sysbus_init_irq(sbd, &s->irq_ir);
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}
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static void crf_finalize(Object *obj)
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{
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XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_crf = {
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.name = TYPE_XLNX_ZYNQMP_CRF,
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.version_id = 1,
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@@ -255,7 +250,6 @@ static const TypeInfo crf_info = {
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.instance_size = sizeof(XlnxZynqMPCRF),
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.class_init = crf_class_init,
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.instance_init = crf_init,
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.instance_finalize = crf_finalize,
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};
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static void crf_register_types(void)
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+3
-10
@@ -456,8 +456,9 @@ static void bbram_ctrl_init(Object *obj)
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{
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XlnxBBRam *s = XLNX_BBRAM(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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s->reg_array =
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reg_array =
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register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
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ARRAY_SIZE(bbram_ctrl_regs_info),
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s->regs_info, s->regs,
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@@ -465,17 +466,10 @@ static void bbram_ctrl_init(Object *obj)
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XLNX_BBRAM_ERR_DEBUG,
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R_MAX * 4);
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sysbus_init_mmio(sbd, &s->reg_array->mem);
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sysbus_init_mmio(sbd, ®_array->mem);
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sysbus_init_irq(sbd, &s->irq_bbram);
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}
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static void bbram_ctrl_finalize(Object *obj)
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{
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XlnxBBRam *s = XLNX_BBRAM(obj);
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register_finalize_block(s->reg_array);
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}
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static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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@@ -542,7 +536,6 @@ static const TypeInfo bbram_ctrl_info = {
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.instance_size = sizeof(XlnxBBRam),
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.class_init = bbram_ctrl_class_init,
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.instance_init = bbram_ctrl_init,
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.instance_finalize = bbram_ctrl_finalize,
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};
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static void bbram_ctrl_register_types(void)
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@@ -728,7 +728,6 @@ static void efuse_ctrl_finalize(Object *obj)
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{
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XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
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register_finalize_block(s->reg_array);
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g_free(s->extra_pg0_lock_spec);
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}
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@@ -816,13 +816,6 @@ static void zynqmp_efuse_init(Object *obj)
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sysbus_init_irq(sbd, &s->irq);
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}
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static void zynqmp_efuse_finalize(Object *obj)
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{
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XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
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register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_efuse = {
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.name = TYPE_XLNX_ZYNQMP_EFUSE,
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.version_id = 1,
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@@ -857,7 +850,6 @@ static const TypeInfo efuse_info = {
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.instance_size = sizeof(XlnxZynqMPEFuse),
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.class_init = zynqmp_efuse_class_init,
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.instance_init = zynqmp_efuse_init,
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.instance_finalize = zynqmp_efuse_finalize,
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};
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static void efuse_register_types(void)
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@@ -533,7 +533,6 @@ REG32(VERSAL2_RST_OCM, 0x3d8)
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struct XlnxVersalCRLBase {
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SysBusDevice parent_obj;
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RegisterInfoArray *reg_array;
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uint32_t *regs;
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};
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@@ -90,7 +90,6 @@ typedef struct XlnxXramCtrl {
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unsigned int encoded_size;
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} cfg;
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RegisterInfoArray *reg_array;
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uint32_t regs[XRAM_CTRL_R_MAX];
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RegisterInfo regs_info[XRAM_CTRL_R_MAX];
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} XlnxXramCtrl;
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@@ -85,7 +85,6 @@ struct XlnxZynqMPAPUCtrl {
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uint8_t cpu_pwrdwn_req;
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uint8_t cpu_in_wfi;
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RegisterInfoArray *reg_array;
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uint32_t regs[APU_R_MAX];
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RegisterInfo regs_info[APU_R_MAX];
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};
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@@ -203,7 +203,6 @@ struct XlnxZynqMPCRF {
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MemoryRegion iomem;
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qemu_irq irq_ir;
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RegisterInfoArray *reg_array;
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uint32_t regs[CRF_R_MAX];
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RegisterInfo regs_info[CRF_R_MAX];
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};
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@@ -47,7 +47,6 @@ struct XlnxBBRam {
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bool bbram8_wo;
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bool blk_ro;
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RegisterInfoArray *reg_array;
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uint32_t regs[RMAX_XLNX_BBRAM];
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RegisterInfo regs_info[RMAX_XLNX_BBRAM];
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};
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