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target/i386: clear CPU_INTERRUPT_SIPI for all accelerators

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Similar to what commit df32e5c5 did for TCG; fixes boot with multiple
processors on WHPX and probably more accelerators

Fixes: df32e5c568 ("i386/cpu: Prevent delivering SIPI during SMM in TCG mode", 2025-10-14)
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3178
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
2025-10-24 09:18:43 +02:00
parent 9a2aa6bfeb
commit d5e1d2dea1
4 changed files with 4 additions and 0 deletions
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target/i386/hvf/x86hvf.c
+1
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@@ -446,6 +446,7 @@ int hvf_process_events(CPUState *cs)
cs->halted = 0;
}
if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_SIPI);
cpu_synchronize_state(cs);
do_cpu_sipi(cpu);
}
target/i386/kvm/kvm.c
+1
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@@ -5659,6 +5659,7 @@ int kvm_arch_process_async_events(CPUState *cs)
cs->halted = 0;
}
if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_SIPI);
kvm_cpu_synchronize_state(cs);
do_cpu_sipi(cpu);
}
target/i386/nvmm/nvmm-all.c
+1
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@@ -709,6 +709,7 @@ nvmm_vcpu_loop(CPUState *cpu)
cpu->halted = false;
}
if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_SIPI);
nvmm_cpu_synchronize_state(cpu);
do_cpu_sipi(x86_cpu);
}
target/i386/whpx/whpx-all.c
+1
View File
@@ -1621,6 +1621,7 @@ static void whpx_vcpu_process_async_events(CPUState *cpu)
}
if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {
cpu_reset_interrupt(cpu, CPU_INTERRUPT_SIPI);
whpx_cpu_synchronize_state(cpu);
do_cpu_sipi(x86_cpu);
}