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tcg/tci: Introduce INDEX_op_tci_qemu_{ld,st}_rrr

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Since d182123974, the number of bits in a MemOpIdx tops out at 17.
which won't fit in the TCI rrm format, thus an assertion failure.
Introduce new opcodes that take the MemOpIdx from a register, as
we already do for qemu_ld2 and qemu_st2.

Fixes: d182123974 ("include/exec/memopidx: Adjust for 32 mmu indexes")
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
2025-12-01 14:02:41 -08:00
parent 41706d3e72
commit 92cf74baf4
3 changed files with 33 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tcg/tci.c
+19
View File
@@ -794,12 +794,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = regs[r1];
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
break;
case INDEX_op_tci_qemu_ld_rrr:
tci_args_rrr(insn, &r0, &r1, &r2);
taddr = regs[r1];
oi = regs[r2];
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
break;
case INDEX_op_qemu_st:
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
break;
case INDEX_op_tci_qemu_st_rrr:
tci_args_rrr(insn, &r0, &r1, &r2);
taddr = regs[r1];
oi = regs[r2];
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
break;
case INDEX_op_qemu_ld2:
tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
@@ -1050,6 +1062,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), oi);
break;
case INDEX_op_tci_qemu_ld_rrr:
case INDEX_op_tci_qemu_st_rrr:
tci_args_rrr(insn, &r0, &r1, &r2);
info->fprintf_func(info->stream, "%-12s %s, %s, %s",
op_name, str_r(r0), str_r(r1), str_r(r2));
break;
case INDEX_op_qemu_ld2:
case INDEX_op_qemu_st2:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
tcg/tci/tcg-target-opc.h.inc
+2
View File
@@ -13,3 +13,5 @@ DEF(tci_rotl32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
DEF(tci_rotr32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT)
DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT)
DEF(tci_qemu_ld_rrr, 1, 2, 0, TCG_OPF_NOT_PRESENT)
DEF(tci_qemu_st_rrr, 0, 3, 0, TCG_OPF_NOT_PRESENT)
tcg/tci/tcg-target.c.inc
+12 -2
View File
@@ -1188,7 +1188,12 @@ static const TCGOutOpStore outop_st = {
static void tgen_qemu_ld(TCGContext *s, TCGType type, TCGReg data,
TCGReg addr, MemOpIdx oi)
{
tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi);
if (oi & ~0xffff) {
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi);
tcg_out_op_rrr(s, INDEX_op_tci_qemu_ld_rrr, data, addr, TCG_REG_TMP);
} else {
tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi);
}
}
static const TCGOutOpQemuLdSt outop_qemu_ld = {
@@ -1213,7 +1218,12 @@ static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = {
static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data,
TCGReg addr, MemOpIdx oi)
{
tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi);
if (oi & ~0xffff) {
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi);
tcg_out_op_rrr(s, INDEX_op_tci_qemu_st_rrr, data, addr, TCG_REG_TMP);
} else {
tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi);
}
}
static const TCGOutOpQemuLdSt outop_qemu_st = {