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update core

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This commit is contained in:
Logan McNaughton committed 2022-08-02 13:52:37 -06:00
1 parent d35199759d
commit 77bb0b6441
33 files changed
+166 -225
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mupen64plus-core/data/mupen64plus.ini
-17
View File
@@ -3658,7 +3658,6 @@ Players=1
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[AF740B224E5DD0BD09F7254811559ADF]
GoodName=Disney's Tarzan (E) [h1C]
@@ -3672,7 +3671,6 @@ Players=1
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[DF3CDD959E8C63B45F557FC197CE0E63]
GoodName=Disney's Tarzan (G) [!]
@@ -3694,7 +3692,6 @@ Players=1
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[C56AD8ABD0FB5EFEF1FA0229F9A2EFF0]
GoodName=Disney's Tarzan (U) [f1] (PAL)
@@ -6453,7 +6450,6 @@ Players=4
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[1F57194EA272CF5DB500D228E9C94D75]
GoodName=Hydro Thunder (E) [f1] (NTSC)
@@ -6467,7 +6463,6 @@ Players=4
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[54F43E6B68782E98CAABEA5E7976B2BE]
GoodName=Hydro Thunder (U) [!]
@@ -6476,7 +6471,6 @@ Players=4
SaveType=None
Mempak=Yes
Rumble=Yes
RspForceInterrupt=1
[22AAD544C062FB8A2DC6B2DEB32DE188]
GoodName=Hydro Thunder (U) [b1]
@@ -9048,8 +9042,6 @@ Status=3
SaveType=Eeprom 4KB
Players=4
Mempak=Yes
; Multiplayer Timing Fix
Cheat0=81001A1C 2409,81001A1E 0002,81001C74 240A,81001C76 0002
[EC0FAE8002AC6356E0470CE21BFEFA4F]
GoodName=Mario Kart 64 (E) (V1.0) (Super W00ting Hack)
@@ -9078,8 +9070,6 @@ Status=3
SaveType=Eeprom 4KB
Players=4
Mempak=Yes
; Multiplayer Timing Fix
Cheat0=81001A1C 2409,81001A1E 0002,81001C74 240A,81001C76 0002
[2A64632C71FFB90DF3AE83836DEDD7A6]
GoodName=Mario Kart 64 (E) (V1.1) [T+Ita_Cattivik66][b1]
@@ -9098,8 +9088,6 @@ Status=3
SaveType=Eeprom 4KB
Players=4
Mempak=Yes
; Multiplayer Timing Fix
Cheat0=81001A1C 2409,81001A1E 0002,81001C74 240A,81001C76 0002
[8FD3C06ED13CD27BB3D664C92A455AA8]
GoodName=Mario Kart 64 (J) (V1.0) [T+Ita_Cattivik66][b1]
@@ -9128,8 +9116,6 @@ Status=3
SaveType=Eeprom 4KB
Players=4
Mempak=Yes
; Multiplayer Timing Fix
Cheat0=81001A1C 2409,81001A1E 0002,81001C74 240A,81001C76 0002
[231F0134D2899C08930F6E34682D2C0B]
GoodName=Mario Kart 64 (J) (V1.1) [b1]
@@ -9153,8 +9139,6 @@ Status=3
SaveType=Eeprom 4KB
Players=4
Mempak=Yes
; Multiplayer Timing Fix
Cheat0=81001A38 2409,81001A3A 0002,81001A3C 2409,81001A3E 0002,81001C90 240A,81001C92 0002,81001C94 240A,81001C96 0002
[B63346465FE70DA3B1E7493CE5A15A31]
GoodName=Mario Kart 64 (U) (Super W00ting Hack)
@@ -10640,7 +10624,6 @@ CRC=3FFE80F4 A7C15F7E
Players=4
SaveType=None
Mempak=Yes
RspForceInterrupt=1
[76DB89759121710C416ECFB1736B5E39]
GoodName=NBA Showtime - NBA on NBC (U) [f1] (Country Check)
mupen64plus-core/src/api/frontend.c
-1
View File
@@ -425,7 +425,6 @@ EXPORT m64p_error CALL CoreGetRomSettings(m64p_rom_settings *RomSettings, int Ro
RomSettings->transferpak = entry->transferpak;
RomSettings->mempak = entry->mempak;
RomSettings->disableextramem = entry->disableextramem;
RomSettings->rspforceinterrupt = entry->rspforceinterrupt;
RomSettings->savetype = entry->savetype;
return M64ERR_SUCCESS;
mupen64plus-core/src/api/m64p_types.h
-1
View File
@@ -280,7 +280,6 @@ typedef struct
unsigned char mempak; /* 0 - No, 1 - Yes boolean for memory pak support. */
unsigned char biopak; /* 0 - No, 1 - Yes boolean for bio pak support. */
unsigned char disableextramem; /* 0 - No, 1 - Yes boolean for disabling 4MB expansion RAM pack */
unsigned char rspforceinterrupt;
} m64p_rom_settings;
/* ----------------------------------------- */
mupen64plus-core/src/device/cart/cart.c
+4 -5
View File
@@ -167,7 +167,6 @@ void read_cart_dom2(void* opaque, uint32_t address, uint32_t* value)
cart->use_flashram = 1;
read_flashram(&cart->flashram, address, value);
}
cp0_add_cycles(cart->cart_rom.r4300, pi_calculate_cycles(cart->cart_rom.pi, 2, 4, 0));
}
void write_cart_dom2(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -204,7 +203,7 @@ uint32_t cart_dom2_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_add
{
flashram_dma_read(&cart->flashram, dram, dram_addr, cart_addr, length);
}
return pi_calculate_cycles(cart->cart_rom.pi, 2, length, 1);
return pi_calculate_cycles(cart->cart_rom.pi, 2, length);
}
uint32_t cart_dom2_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
@@ -220,20 +219,20 @@ uint32_t cart_dom2_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, ui
{
flashram_dma_write(&cart->flashram, dram, dram_addr, cart_addr, length);
}
return pi_calculate_cycles(cart->cart_rom.pi, 2, length, 1);
return pi_calculate_cycles(cart->cart_rom.pi, 2, length);
}
uint32_t cart_dom3_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
{
struct cart* cart = (struct cart*)opaque;
cart_rom_dma_read(&cart->cart_rom, dram, dram_addr, cart_addr, length);
return pi_calculate_cycles(cart->cart_rom.pi, 1, length, 1);
return pi_calculate_cycles(cart->cart_rom.pi, 1, length);
}
uint32_t cart_dom3_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
{
struct cart* cart = (struct cart*)opaque;
cart_rom_dma_write(&cart->cart_rom, dram, dram_addr, cart_addr, length);
return pi_calculate_cycles(cart->cart_rom.pi, 1, length, 1);
return pi_calculate_cycles(cart->cart_rom.pi, 1, length);
}
mupen64plus-core/src/device/cart/cart_rom.c
+4 -4
View File
@@ -66,7 +66,7 @@ void read_cart_rom(void* opaque, uint32_t address, uint32_t* value)
{
*value = *(uint32_t*)(cart_rom->rom + addr);
}
cp0_add_cycles(cart_rom->r4300, pi_calculate_cycles(cart_rom->pi, 1, 4, 0));
cp0_dcm_interlock(cart_rom->r4300, pi_calculate_cycles(cart_rom->pi, 1, 4));
}
void write_cart_rom(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -79,7 +79,7 @@ void write_cart_rom(void* opaque, uint32_t address, uint32_t value, uint32_t mas
/* Mark IO as busy */
cart_rom->pi->regs[PI_STATUS_REG] |= PI_STATUS_IO_BUSY;
add_interrupt_event(&cart_rom->r4300->cp0, PI_INT, pi_calculate_cycles(cart_rom->pi, 1, 4, 0) / 2);
add_interrupt_event(&cart_rom->r4300->cp0, PI_INT, pi_calculate_cycles(cart_rom->pi, 1, 4) / 2);
}
uint32_t cart_rom_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
@@ -88,7 +88,7 @@ uint32_t cart_rom_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr
cart_addr &= CART_ROM_ADDR_MASK;
DebugMessage(M64MSG_WARNING, "DMA Writing to CART_ROM: 0x%" PRIX32 " -> 0x%" PRIX32 " (0x%" PRIX32 ")", dram_addr, cart_addr, length);
return pi_calculate_cycles(cart_rom->pi, 1, length, 1);
return pi_calculate_cycles(cart_rom->pi, 1, length);
}
uint32_t cart_rom_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
@@ -122,6 +122,6 @@ uint32_t cart_rom_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, uin
/* invalidate cached code */
invalidate_r4300_cached_code(cart_rom->r4300, 0x80000000 + dram_addr, length);
invalidate_r4300_cached_code(cart_rom->r4300, 0xa0000000 + dram_addr, length);
return pi_calculate_cycles(cart_rom->pi, 1, length, 1);
return pi_calculate_cycles(cart_rom->pi, 1, length);
}
mupen64plus-core/src/device/dd/dd_controller.c
+3 -4
View File
@@ -366,7 +366,6 @@ void read_dd_regs(void* opaque, uint32_t address, uint32_t* value)
}
} break;
}
cp0_uncached_read(dd->r4300);
}
void write_dd_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -543,7 +542,7 @@ void read_dd_rom(void* opaque, uint32_t address, uint32_t* value)
*value = dd->rom[addr];
DebugMessage(M64MSG_VERBOSE, "DD ROM: %08X -> %08x", address, *value);
cp0_add_cycles(dd->r4300, pi_calculate_cycles(dd->pi, 1, 4, 0));
cp0_dcm_interlock(dd->r4300, pi_calculate_cycles(dd->pi, 1, 4));
}
void write_dd_rom(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -556,7 +555,7 @@ uint32_t dd_dom_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr,
struct dd_controller* dd = (struct dd_controller*)opaque;
uint8_t* mem;
size_t i;
uint32_t cycles = pi_calculate_cycles(dd->pi, 1, length, 1);
uint32_t cycles = pi_calculate_cycles(dd->pi, 1, length);
DebugMessage(M64MSG_VERBOSE, "DD DMA read dram=%08x cart=%08x length=%08x",
dram_addr, cart_addr, length);
@@ -586,7 +585,7 @@ uint32_t dd_dom_dma_write(void* opaque, uint8_t* dram, uint32_t dram_addr, uint3
struct dd_controller* dd = (struct dd_controller*)opaque;
const uint8_t* mem;
size_t i;
uint32_t cycles = pi_calculate_cycles(dd->pi, 1, length, 1);
uint32_t cycles = pi_calculate_cycles(dd->pi, 1, length);
DebugMessage(M64MSG_VERBOSE, "DD DMA write dram=%08x cart=%08x length=%08x",
dram_addr, cart_addr, length);
mupen64plus-core/src/device/device.c
+4 -8
View File
@@ -38,10 +38,8 @@
static void read_open_bus(void* opaque, uint32_t address, uint32_t* value)
{
struct r4300_core* r4300 = (struct r4300_core*)opaque;
*value = (address & 0xffff);
*value |= (*value << 16);
cp0_uncached_read(r4300);
}
static void write_open_bus(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -87,8 +85,6 @@ void init_device(struct device* dev,
int no_compiled_jump,
int randomize_interrupt,
uint32_t start_address,
/* rsp */
uint32_t rsp_force_interrupt,
/* ai */
void* aout, const struct audio_out_backend_interface* iaout,
/* rdram */
@@ -134,7 +130,7 @@ void init_device(struct device* dev,
#define A(x,m) (x), (x) | (m)
struct mem_mapping mappings[] = {
/* clear mappings */
{ 0x00000000, 0xffffffff, M64P_MEM_NOTHING, { &dev->r4300, RW(open_bus) } },
{ 0x00000000, 0xffffffff, M64P_MEM_NOTHING, { NULL, RW(open_bus) } },
/* memory map */
{ A(MM_RDRAM_DRAM, dram_size-1), M64P_MEM_RDRAM, { &dev->rdram, RW(rdram_dram) } },
{ A(MM_RDRAM_REGS, 0xfffff), M64P_MEM_RDRAMREG, { &dev->rdram, RW(rdram_regs) } },
@@ -149,8 +145,8 @@ void init_device(struct device* dev,
{ A(MM_PI_REGS, 0xffff), M64P_MEM_PI, { &dev->pi, RW(pi_regs) } },
{ A(MM_RI_REGS, 0xffff), M64P_MEM_RI, { &dev->ri, RW(ri_regs) } },
{ A(MM_SI_REGS, 0xffff), M64P_MEM_SI, { &dev->si, RW(si_regs) } },
{ A(MM_DOM2_ADDR1, 0xffffff), M64P_MEM_NOTHING, { &dev->r4300, RW(open_bus) } },
{ A(MM_DD_ROM, 0x1ffffff), M64P_MEM_NOTHING, { &dev->r4300, RW(open_bus) } },
{ A(MM_DOM2_ADDR1, 0xffffff), M64P_MEM_NOTHING, { NULL, RW(open_bus) } },
{ A(MM_DD_ROM, 0x1ffffff), M64P_MEM_NOTHING, { NULL, RW(open_bus) } },
{ A(MM_DOM2_ADDR2, 0x1ffff), M64P_MEM_FLASHRAMSTAT, { &dev->cart, RW(cart_dom2) } },
{ A(MM_IS_VIEWER, 0xfff), M64P_MEM_NOTHING, { &dev->is, RW(is_viewer) } },
{ A(MM_CART_ROM, rom_size-1), M64P_MEM_ROM, { &dev->cart.cart_rom, RW(cart_rom) } },
@@ -182,7 +178,7 @@ void init_device(struct device* dev,
init_r4300(&dev->r4300, &dev->mem, &dev->mi, &dev->rdram, interrupt_handlers,
emumode, no_compiled_jump, randomize_interrupt, start_address);
init_rdp(&dev->dp, &dev->sp, &dev->mi, &dev->mem, &dev->rdram, &dev->r4300);
init_rsp(&dev->sp, mem_base_u32(base, MM_RSP_MEM), &dev->mi, &dev->dp, &dev->ri, rsp_force_interrupt);
init_rsp(&dev->sp, mem_base_u32(base, MM_RSP_MEM), &dev->mi, &dev->dp, &dev->ri);
init_ai(&dev->ai, &dev->mi, &dev->ri, &dev->vi, aout, iaout);
init_mi(&dev->mi, &dev->r4300);
init_pi(&dev->pi,
mupen64plus-core/src/device/device.h
-2
View File
@@ -123,8 +123,6 @@ void init_device(struct device* dev,
int no_compiled_jump,
int randomize_interrupt,
uint32_t start_address,
/* rsp */
uint32_t rsp_force_interrupt,
/* ai */
void* aout, const struct audio_out_backend_interface* iaout,
/* rdram */
mupen64plus-core/src/device/pif/pif.c
-1
View File
@@ -291,7 +291,6 @@ void read_pif_mem(void* opaque, uint32_t address, uint32_t* value)
memcpy(value, pif->base + addr, sizeof(*value));
if (addr >= PIF_ROM_SIZE)
*value = tohl(*value);
cp0_uncached_read(pif->r4300);
}
void write_pif_mem(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/r4300/cached_interp.c
-6
View File
@@ -85,7 +85,6 @@ void cached_interp_##name(void) \
UPDATE_DEBUGGER(); \
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr); \
(*r4300_pc_struct(r4300))->ops(); \
cp0_add_cycles(r4300, r4300->cp0.instr_count); \
r4300->delay_slot=0; \
if (take_jump && !r4300->skip_jump) \
{ \
@@ -118,7 +117,6 @@ void cached_interp_##name##_OUT(void) \
UPDATE_DEBUGGER(); \
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr); \
(*r4300_pc_struct(r4300))->ops(); \
cp0_add_cycles(r4300, r4300->cp0.instr_count); \
r4300->delay_slot=0; \
if (take_jump && !r4300->skip_jump) \
{ \
@@ -204,7 +202,6 @@ Used by dynarec only, check should be unnecessary
*/
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr);
(*r4300_pc_struct(r4300))->ops();
cp0_add_cycles(r4300, r4300->cp0.instr_count);
}
else
{
@@ -222,7 +219,6 @@ Used by dynarec only, check should be unnecessary
{
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr);
(*r4300_pc_struct(r4300))->ops();
cp0_add_cycles(r4300, r4300->cp0.instr_count);
r4300->cached_interp.actual = blk;
(*r4300_pc_struct(r4300)) = inst+1;
}
@@ -255,7 +251,6 @@ called before NOTCOMPILED would have been executed
*/
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr);
(*r4300_pc_struct(r4300))->ops();
cp0_add_cycles(r4300, r4300->cp0.instr_count);
}
void cached_interp_NOTCOMPILED2(void)
@@ -1005,6 +1000,5 @@ void run_cached_interpreter(struct r4300_core* r4300)
#endif
icache_fetch(r4300, (*r4300_pc_struct(r4300))->addr);
(*r4300_pc_struct(r4300))->ops();
cp0_add_cycles(r4300, r4300->cp0.instr_count);
}
}
mupen64plus-core/src/device/r4300/cp0.c
+25 -12
View File
@@ -72,7 +72,6 @@ void poweron_cp0(struct cp0* cp0)
*cp0_next_interrupt = 0;
*cp0_cycle_count = 0;
cp0->half_count = 0;
cp0->instr_count = 1;
cp0->last_addr = UINT32_C(0xbfc00000);
init_interrupt(cp0);
@@ -125,14 +124,7 @@ int check_cop1_unusable(struct r4300_core* r4300)
return 0;
}
void cp0_set_cycles(struct r4300_core* r4300, uint32_t cycles)
{
struct cp0* cp0 = &r4300->cp0;
if (cycles > cp0->instr_count)
cp0->instr_count = cycles;
}
void cp0_add_cycles(struct r4300_core* r4300, uint32_t cycles)
static void cp0_add_cycles(struct r4300_core* r4300, uint32_t cycles)
{
struct cp0* cp0 = &r4300->cp0;
uint32_t* cp0_regs = r4300_cp0_regs(cp0);
@@ -148,18 +140,39 @@ void cp0_add_cycles(struct r4300_core* r4300, uint32_t cycles)
*r4300_cp0_cycle_count(cp0) += count;
}
void cp0_cached_read(struct r4300_core* r4300)
void cp0_base_cycle(struct r4300_core* r4300)
{
cp0_add_cycles(r4300, 1);
}
void cp0_uncached_read(struct r4300_core* r4300)
void cp0_mci_interlock(struct r4300_core* r4300, uint32_t cycles)
{
cp0_add_cycles(r4300, 7);
cp0_add_cycles(r4300, cycles - 1);
}
void cp0_itm_interlock(struct r4300_core* r4300)
{
cp0_add_cycles(r4300, 3);
}
void cp0_dcm_interlock(struct r4300_core* r4300, uint32_t cycles)
{
cp0_add_cycles(r4300, cycles);
}
void cp0_dcb_interlock(struct r4300_core* r4300, uint32_t cycles)
{
cp0_add_cycles(r4300, cycles);
}
void cp0_icb_interlock(struct r4300_core* r4300, uint32_t cycles)
{
cp0_add_cycles(r4300, cycles);
}
static void exception_epilog(struct r4300_core* r4300)
{
cp0_add_cycles(r4300, 2);
#ifndef NO_ASM
#ifndef NEW_DYNAREC
if (r4300->emumode == EMUMODE_DYNAREC)
mupen64plus-core/src/device/r4300/cp0.h
+6 -6
View File
@@ -204,7 +204,6 @@ struct cp0
struct tlb tlb;
uint8_t half_count;
uint32_t instr_count;
};
#ifndef NEW_DYNAREC
@@ -231,11 +230,12 @@ int* r4300_cp0_cycle_count(struct cp0* cp0);
int check_cop1_unusable(struct r4300_core* r4300);
void cp0_set_cycles(struct r4300_core* r4300, uint32_t cycles);
void cp0_add_cycles(struct r4300_core* r4300, uint32_t cycles);
void cp0_cached_read(struct r4300_core* r4300);
void cp0_uncached_read(struct r4300_core* r4300);
void cp0_base_cycle(struct r4300_core* r4300);
void cp0_mci_interlock(struct r4300_core* r4300, uint32_t cycles);
void cp0_dcb_interlock(struct r4300_core* r4300, uint32_t cycles);
void cp0_icb_interlock(struct r4300_core* r4300, uint32_t cycles);
void cp0_itm_interlock(struct r4300_core* r4300);
void cp0_dcm_interlock(struct r4300_core* r4300, uint32_t cycles);
void TLB_refill_exception(struct r4300_core* r4300, uint32_t address, int w);
void exception_general(struct r4300_core* r4300);
mupen64plus-core/src/device/r4300/dcache.c
+4 -3
View File
@@ -33,6 +33,7 @@ void poweron_dcache(struct datacache *lines)
void dcache_writeback(struct r4300_core* r4300, struct datacache *line)
{
cp0_dcb_interlock(r4300, 20);
line->dirty = 0;
uint32_t cache_address = line->tag | line->index;
invalidate_r4300_cached_code(r4300, cache_address, 16);
@@ -52,7 +53,7 @@ uint32_t dcache_hit(struct datacache *line, uint32_t address)
static void dcache_fill(struct datacache *line, struct r4300_core* r4300, uint32_t address)
{
cp0_add_cycles(r4300, 5);
cp0_dcb_interlock(r4300, 5);
line->valid = 1;
line->dirty = 0;
line->tag = address & ~UINT32_C(0xFFF);
@@ -74,8 +75,6 @@ void dcache_read32(struct r4300_core* r4300, uint32_t address, uint32_t *value)
dcache_writeback(r4300, line);
dcache_fill(line, r4300, address);
}
else
cp0_cached_read(r4300);
*value = line->words[(address >> 2) & UINT32_C(3)];
}
@@ -88,6 +87,8 @@ void dcache_write32(struct r4300_core* r4300, uint32_t address, uint32_t value,
dcache_writeback(r4300, line);
dcache_fill(line, r4300, address);
}
else
cp0_dcb_interlock(r4300, 1);
masked_write(&line->words[(address >> 2) & UINT32_C(3)], value, mask);
line->dirty = 1;
}
mupen64plus-core/src/device/r4300/icache.c
+7 -5
View File
@@ -33,6 +33,7 @@ void poweron_icache(struct instcache *lines)
void icache_writeback(struct r4300_core* r4300, struct instcache *line)
{
cp0_icb_interlock(r4300, 24);
uint32_t cache_address = line->tag | line->index;
invalidate_r4300_cached_code(r4300, cache_address, 32);
invalidate_r4300_cached_code(r4300, cache_address ^ UINT32_C(0x20000000), 32);
@@ -55,7 +56,7 @@ uint32_t icache_hit(struct instcache *line, uint32_t address)
void icache_fill(struct instcache *line, struct r4300_core* r4300, uint32_t address)
{
cp0_add_cycles(r4300, 6);
cp0_icb_interlock(r4300, 6);
line->valid = 1;
line->tag = address & ~UINT32_C(0xFFF);
uint32_t cache_address = line->tag | line->index;
@@ -75,15 +76,16 @@ uint32_t* icache_fetch(struct r4300_core* r4300, uint32_t address)
{
struct instcache *line = &r4300->icache[(address >> 5) & UINT32_C(0x1FF)];
uint8_t cached = 0;
r4300->cp0.instr_count = 1;
if (r4300_translate_address(r4300, &address, &cached, 2, 0))
cp0_base_cycle(r4300);
if (r4300_translate_address(r4300, &address, &cached, 2))
{
cp0_itm_interlock(r4300);
return NULL;
}
if (cached)
{
if(!icache_hit(line, address))
icache_fill(line, r4300, address);
else
cp0_cached_read(r4300);
return &line->words[address >> 2 & 7];
}
else
mupen64plus-core/src/device/r4300/mips_instructions.def
+46 -47
View File
@@ -591,7 +591,6 @@ DECLARE_INSTRUCTION(NOR)
{
DECLARE_R4300
rrd = ~(rrs | rrt);
cp0_set_cycles(r4300, 57);
ADD_TO_PC(1);
}
@@ -724,7 +723,7 @@ DECLARE_INSTRUCTION(MULT)
temp = rrs32 * (int64_t)rrt32;
*r4300_mult_hi(r4300) = temp >> 32;
*r4300_mult_lo(r4300) = SE32(temp);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -735,7 +734,7 @@ DECLARE_INSTRUCTION(MULTU)
temp = (uint32_t) rrs * (uint64_t) ((uint32_t) rrt);
*r4300_mult_hi(r4300) = (int64_t) temp >> 32;
*r4300_mult_lo(r4300) = SE32(temp);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -783,7 +782,7 @@ DECLARE_INSTRUCTION(DMULT)
if (!*r4300_mult_lo(r4300)) { (*r4300_mult_hi(r4300))++; }
else { *r4300_mult_lo(r4300) = ~*r4300_mult_lo(r4300) + 1; }
}
cp0_set_cycles(r4300, 8);
cp0_mci_interlock(r4300, 8);
ADD_TO_PC(1);
}
@@ -812,7 +811,7 @@ DECLARE_INSTRUCTION(DMULTU)
*r4300_mult_lo(r4300) = result1 | (result2 << 32);
*r4300_mult_hi(r4300) = (result3 & UINT64_C(0xFFFFFFFF)) | (result4 << 32);
cp0_set_cycles(r4300, 8);
cp0_mci_interlock(r4300, 8);
ADD_TO_PC(1);
}
@@ -837,7 +836,7 @@ DECLARE_INSTRUCTION(DIV)
*r4300_mult_lo(r4300) = rrs32 < 0 ? 1 : -1;
*r4300_mult_hi(r4300) = SE32(rrs32);
}
cp0_set_cycles(r4300, 37);
cp0_mci_interlock(r4300, 37);
ADD_TO_PC(1);
}
@@ -854,7 +853,7 @@ DECLARE_INSTRUCTION(DIVU)
*r4300_mult_lo(r4300) = -1;
*r4300_mult_hi(r4300) = SE32(rrs32);
}
cp0_set_cycles(r4300, 37);
cp0_mci_interlock(r4300, 37);
ADD_TO_PC(1);
}
@@ -879,7 +878,7 @@ DECLARE_INSTRUCTION(DDIV)
*r4300_mult_lo(r4300) = rrs < 0 ? 1 : -1;
*r4300_mult_hi(r4300) = rrs;
}
cp0_set_cycles(r4300, 69);
cp0_mci_interlock(r4300, 69);
ADD_TO_PC(1);
}
@@ -896,7 +895,7 @@ DECLARE_INSTRUCTION(DDIVU)
*r4300_mult_lo(r4300) = -1;
*r4300_mult_hi(r4300) = rrs;
}
cp0_set_cycles(r4300, 69);
cp0_mci_interlock(r4300, 69);
ADD_TO_PC(1);
}
@@ -969,7 +968,7 @@ DECLARE_INSTRUCTION(CACHE)
{
DECLARE_R4300
uint32_t lslfaddr = (uint32_t) r4300_regs(r4300)[lfbase] + lfoffset;
if (r4300_translate_address(r4300, &lslfaddr, &(uint8_t){0}, 2, 0))
if (r4300_translate_address(r4300, &lslfaddr, &(uint8_t){0}, 2))
return; // TLB exception
uint32_t* cp0_regs = r4300_cp0_regs(&r4300->cp0);
const unsigned char lslfft = lfft;
@@ -1530,7 +1529,7 @@ DECLARE_INSTRUCTION(ABS_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
abs_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1539,7 +1538,7 @@ DECLARE_INSTRUCTION(ABS_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
abs_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1548,7 +1547,7 @@ DECLARE_INSTRUCTION(ADD_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
add_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1557,7 +1556,7 @@ DECLARE_INSTRUCTION(ADD_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
add_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1570,7 +1569,7 @@ DECLARE_INSTRUCTION(DIV_S)
DebugMessage(M64MSG_ERROR, "DIV_S by 0");
}
div_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 29);
cp0_mci_interlock(r4300, 29);
ADD_TO_PC(1);
}
@@ -1588,7 +1587,7 @@ DECLARE_INSTRUCTION(DIV_D)
//return;
}
div_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 58);
cp0_mci_interlock(r4300, 58);
ADD_TO_PC(1);
}
@@ -1613,7 +1612,7 @@ DECLARE_INSTRUCTION(MUL_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
mul_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1622,7 +1621,7 @@ DECLARE_INSTRUCTION(MUL_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
mul_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 8);
cp0_mci_interlock(r4300, 8);
ADD_TO_PC(1);
}
@@ -1647,7 +1646,7 @@ DECLARE_INSTRUCTION(SQRT_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
sqrt_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 29);
cp0_mci_interlock(r4300, 29);
ADD_TO_PC(1);
}
@@ -1656,7 +1655,7 @@ DECLARE_INSTRUCTION(SQRT_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
sqrt_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 58);
cp0_mci_interlock(r4300, 58);
ADD_TO_PC(1);
}
@@ -1665,7 +1664,7 @@ DECLARE_INSTRUCTION(SUB_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
sub_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cfft], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1674,7 +1673,7 @@ DECLARE_INSTRUCTION(SUB_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
sub_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cfft], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 3);
cp0_mci_interlock(r4300, 3);
ADD_TO_PC(1);
}
@@ -1683,7 +1682,7 @@ DECLARE_INSTRUCTION(TRUNC_W_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
trunc_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1692,7 +1691,7 @@ DECLARE_INSTRUCTION(TRUNC_W_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
trunc_w_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1701,7 +1700,7 @@ DECLARE_INSTRUCTION(TRUNC_L_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
trunc_l_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1710,7 +1709,7 @@ DECLARE_INSTRUCTION(TRUNC_L_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
trunc_l_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1719,7 +1718,7 @@ DECLARE_INSTRUCTION(ROUND_W_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
round_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1728,7 +1727,7 @@ DECLARE_INSTRUCTION(ROUND_W_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
round_w_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1737,7 +1736,7 @@ DECLARE_INSTRUCTION(ROUND_L_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
round_l_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1746,7 +1745,7 @@ DECLARE_INSTRUCTION(ROUND_L_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
round_l_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1755,7 +1754,7 @@ DECLARE_INSTRUCTION(CEIL_W_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
ceil_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1764,7 +1763,7 @@ DECLARE_INSTRUCTION(CEIL_W_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
ceil_w_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1773,7 +1772,7 @@ DECLARE_INSTRUCTION(CEIL_L_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
ceil_l_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1782,7 +1781,7 @@ DECLARE_INSTRUCTION(CEIL_L_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
ceil_l_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1791,7 +1790,7 @@ DECLARE_INSTRUCTION(FLOOR_W_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
floor_w_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1800,7 +1799,7 @@ DECLARE_INSTRUCTION(FLOOR_W_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
floor_w_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1809,7 +1808,7 @@ DECLARE_INSTRUCTION(FLOOR_L_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
floor_l_s((r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1818,7 +1817,7 @@ DECLARE_INSTRUCTION(FLOOR_L_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
floor_l_d((r4300_cp1_regs_double(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1827,7 +1826,7 @@ DECLARE_INSTRUCTION(CVT_S_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_s_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 2);
cp0_mci_interlock(r4300, 2);
ADD_TO_PC(1);
}
@@ -1836,7 +1835,7 @@ DECLARE_INSTRUCTION(CVT_S_W)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_s_w(*r4300_cp1_fcr31(&r4300->cp1), (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1845,7 +1844,7 @@ DECLARE_INSTRUCTION(CVT_S_L)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_s_l(*r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1862,7 +1861,7 @@ DECLARE_INSTRUCTION(CVT_D_W)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_d_w((int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1871,7 +1870,7 @@ DECLARE_INSTRUCTION(CVT_D_L)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_d_l(*r4300_cp1_fcr31(&r4300->cp1), (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffs], (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1880,7 +1879,7 @@ DECLARE_INSTRUCTION(CVT_W_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_w_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1889,7 +1888,7 @@ DECLARE_INSTRUCTION(CVT_W_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_w_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (int32_t*) (r4300_cp1_regs_simple(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1898,7 +1897,7 @@ DECLARE_INSTRUCTION(CVT_L_S)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_l_s(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_simple(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
@@ -1907,7 +1906,7 @@ DECLARE_INSTRUCTION(CVT_L_D)
DECLARE_R4300
if (check_cop1_unusable(r4300)) { return; }
cvt_l_d(*r4300_cp1_fcr31(&r4300->cp1), (r4300_cp1_regs_double(&r4300->cp1))[cffs], (int64_t*) (r4300_cp1_regs_double(&r4300->cp1))[cffd]);
cp0_set_cycles(r4300, 5);
cp0_mci_interlock(r4300, 5);
ADD_TO_PC(1);
}
mupen64plus-core/src/device/r4300/pure_interp.c
-1
View File
@@ -704,7 +704,6 @@ void InterpretOpcode(struct r4300_core* r4300)
RESERVED(r4300, op);
break;
} /* switch ((op >> 26) & 0x3F) */
cp0_add_cycles(r4300, r4300->cp0.instr_count);
}
void run_pure_interpreter(struct r4300_core* r4300)
mupen64plus-core/src/device/r4300/r4300_core.c
+18 -13
View File
@@ -281,22 +281,15 @@ unsigned int get_r4300_emumode(struct r4300_core* r4300)
return r4300->emumode;
}
uint8_t r4300_translate_address(struct r4300_core* r4300, uint32_t* address, uint8_t* cached, uint8_t tlb_mode, uint8_t write)
uint8_t r4300_translate_address(struct r4300_core* r4300, uint32_t* address, uint8_t* cached, uint8_t tlb_mode)
{
if ((*address & UINT32_C(0xc0000000)) != UINT32_C(0x80000000)) {
if (write)
invalidate_r4300_cached_code(r4300, *address, write);
*address = virtual_to_physical_address(r4300, *address, tlb_mode, cached);
if (*address == 0) // TLB exception
return 1;
} else if (!(*address & UINT32_C(0x20000000)))
*cached = 1;
if (write)
{
invalidate_r4300_cached_code(r4300, *address, write);
invalidate_r4300_cached_code(r4300, *address ^ UINT32_C(0x20000000), write);
}
return 0;
}
@@ -304,7 +297,7 @@ uint32_t *fast_mem_access(struct r4300_core* r4300, uint32_t address)
{
/* This code is performance critical, specially on pure interpreter mode.
* Removing error checking saves some time, but the emulator may crash. */
if (r4300_translate_address(r4300, &address, &(uint8_t){0}, 2, 0))
if (r4300_translate_address(r4300, &address, &(uint8_t){0}, 2))
return NULL; // TLB exception
address &= UINT32_C(0x1ffffffc);
@@ -318,7 +311,7 @@ uint32_t *fast_mem_access(struct r4300_core* r4300, uint32_t address)
int r4300_read_aligned_word(struct r4300_core* r4300, uint32_t address, uint32_t* value)
{
uint8_t cached = 0;
if (r4300_translate_address(r4300, &address, &cached, 0, 0))
if (r4300_translate_address(r4300, &address, &cached, 0))
return 0; // TLB exception
if (cached)
@@ -345,7 +338,7 @@ int r4300_read_aligned_dword(struct r4300_core* r4300, uint32_t address, uint64_
DebugMessage(M64MSG_WARNING, "Unaligned dword read %08x", address);
}
if (r4300_translate_address(r4300, &address, &cached, 0, 0))
if (r4300_translate_address(r4300, &address, &cached, 0))
return 0; // TLB exception
if (cached)
@@ -373,9 +366,15 @@ int r4300_read_aligned_dword(struct r4300_core* r4300, uint32_t address, uint64_
int r4300_write_aligned_word(struct r4300_core* r4300, uint32_t address, uint32_t value, uint32_t mask)
{
uint8_t cached = 0;
if (r4300_translate_address(r4300, &address, &cached, 1, 4))
if ((address & UINT32_C(0xc0000000)) != UINT32_C(0x80000000))
invalidate_r4300_cached_code(r4300, address, 4);
if (r4300_translate_address(r4300, &address, &cached, 1))
return 0; // TLB exception
invalidate_r4300_cached_code(r4300, address, 4);
invalidate_r4300_cached_code(r4300, address ^ UINT32_C(0x20000000), 4);
if (cached)
dcache_write32(r4300, address & ~UINT32_C(3), value, mask);
else
@@ -391,6 +390,10 @@ int r4300_write_aligned_word(struct r4300_core* r4300, uint32_t address, uint32_
int r4300_write_aligned_dword(struct r4300_core* r4300, uint32_t address, uint64_t value, uint64_t mask)
{
uint8_t cached = 0;
if ((address & UINT32_C(0xc0000000)) != UINT32_C(0x80000000))
invalidate_r4300_cached_code(r4300, address, 8);
/* XXX: unaligned dword accesses should trigger a address error,
* but inaccurate timing of the core can lead to unaligned address on reset
* so just emit a warning and keep going */
@@ -398,9 +401,11 @@ int r4300_write_aligned_dword(struct r4300_core* r4300, uint32_t address, uint64
DebugMessage(M64MSG_WARNING, "Unaligned dword write %08x", address);
}
if (r4300_translate_address(r4300, &address, &cached, 1, 8))
if (r4300_translate_address(r4300, &address, &cached, 1))
return 0; // TLB exception
invalidate_r4300_cached_code(r4300, address, 8);
invalidate_r4300_cached_code(r4300, address ^ UINT32_C(0x20000000), 8);
if (cached)
{
dcache_write32(r4300, address + 0, value >> 32, mask >> 32);
mupen64plus-core/src/device/r4300/r4300_core.h
+1 -1
View File
@@ -237,7 +237,7 @@ unsigned int get_r4300_emumode(struct r4300_core* r4300);
* Useful for getting fast access to a zone with executable code. */
uint32_t *fast_mem_access(struct r4300_core* r4300, uint32_t address);
uint8_t r4300_translate_address(struct r4300_core* r4300, uint32_t* address, uint8_t* cached, uint8_t tlb_mode, uint8_t write);
uint8_t r4300_translate_address(struct r4300_core* r4300, uint32_t* address, uint8_t* cached, uint8_t tlb_mode);
int r4300_read_aligned_word(struct r4300_core* r4300, uint32_t address, uint32_t* value);
int r4300_read_aligned_dword(struct r4300_core* r4300, uint32_t address, uint64_t* value);
mupen64plus-core/src/device/rcp/ai/ai_controller.c
-1
View File
@@ -181,7 +181,6 @@ void read_ai_regs(void* opaque, uint32_t address, uint32_t* value)
{
*value = ai->regs[reg];
}
cp0_uncached_read(ai->mi->r4300);
}
void write_ai_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/mi/mi_controller.c
-1
View File
@@ -84,7 +84,6 @@ void read_mi_regs(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = mi_reg(address);
*value = mi->regs[reg];
cp0_uncached_read(mi->r4300);
}
void write_mi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/pi/pi_controller.c
+13 -16
View File
@@ -24,6 +24,7 @@
#define M64P_CORE_PROTOTYPES 1
#include <stdint.h>
#include <string.h>
#include <math.h>
#include "api/callbacks.h"
#include "api/m64p_types.h"
@@ -48,7 +49,7 @@ int validate_pi_request(struct pi_controller* pi)
return 1;
}
uint32_t pi_calculate_cycles(struct pi_controller* pi, uint8_t domain, uint32_t length, uint8_t dma)
uint32_t pi_calculate_cycles(struct pi_controller* pi, uint8_t domain, uint32_t length)
{
if (!domain)
{
@@ -56,35 +57,32 @@ uint32_t pi_calculate_cycles(struct pi_controller* pi, uint8_t domain, uint32_t
return length / 8;
}
uint32_t cycles = 0;
uint32_t latency;
uint32_t pulse_width;
uint32_t release;
uint32_t page_size;
uint32_t pages;
uint32_t latency = 0;
uint32_t pulse_width = 0;
uint32_t release = 0;
uint32_t page_size = 0;
uint32_t pages = 0;
if (domain == 1)
{
latency = pi->regs[PI_BSD_DOM1_LAT_REG] + 1;
pulse_width = pi->regs[PI_BSD_DOM1_PWD_REG] + 1;
release = pi->regs[PI_BSD_DOM1_RLS_REG] + 1;
page_size = 2 ^ (pi->regs[PI_BSD_DOM1_PGS_REG] + 2);
page_size = pow(2, (pi->regs[PI_BSD_DOM1_PGS_REG] + 2));
}
else if (domain == 2)
{
latency = pi->regs[PI_BSD_DOM2_LAT_REG] + 1;
pulse_width = pi->regs[PI_BSD_DOM2_PWD_REG] + 1;
release = pi->regs[PI_BSD_DOM2_RLS_REG] + 1;
page_size = 2 ^ (pi->regs[PI_BSD_DOM2_PGS_REG] + 2);
page_size = pow(2, (pi->regs[PI_BSD_DOM2_PGS_REG] + 2));
}
if (dma)
pages = length / page_size;
else
pages = 1;
pages = ceil((double)length / page_size);
cycles += (14 + latency) * pages;
cycles += (pulse_width + release) * (length / 2);
cycles += 5 * pages;
return cycles;
return cycles * 1.5; // Converting RCP clock speed to CPU clock speed
}
static void dma_pi_read(struct pi_controller* pi)
@@ -185,10 +183,10 @@ void poweron_pi(struct pi_controller* pi)
memset(pi->regs, 0, PI_REGS_COUNT*sizeof(uint32_t));
pi->regs[PI_BSD_DOM1_LAT_REG] = 0xFF;
pi->regs[PI_BSD_DOM1_PWD_REG] = 0xFF;
pi->regs[PI_BSD_DOM1_PGS_REG] = 0x03;
pi->regs[PI_BSD_DOM1_RLS_REG] = 0x03;
pi->regs[PI_BSD_DOM2_LAT_REG] = 0xFF;
pi->regs[PI_BSD_DOM2_PWD_REG] = 0xFF;
pi->regs[PI_BSD_DOM2_PGS_REG] = 0x03;
pi->regs[PI_BSD_DOM2_RLS_REG] = 0x03;
}
void read_pi_regs(void* opaque, uint32_t address, uint32_t* value)
@@ -204,7 +202,6 @@ void read_pi_regs(void* opaque, uint32_t address, uint32_t* value)
*value &= 0xFFFFFFFE;
else if (reg == PI_DRAM_ADDR_REG)
*value &= 0xFFFFFE;
cp0_uncached_read(pi->mi->r4300);
}
void write_pi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/pi/pi_controller.h
+1 -1
View File
@@ -108,6 +108,6 @@ void write_pi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask
void pi_end_of_dma_event(void* opaque);
int validate_pi_request(struct pi_controller* pi);
uint32_t pi_calculate_cycles(struct pi_controller* pi, uint8_t domain, uint32_t length, uint8_t dma);
uint32_t pi_calculate_cycles(struct pi_controller* pi, uint8_t domain, uint32_t length);
#endif
mupen64plus-core/src/device/rcp/rdp/rdp_core.c
+9 -3
View File
@@ -88,7 +88,6 @@ void read_dpc_regs(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = dpc_reg(address);
*value = dp->dpc_regs[reg];
cp0_uncached_read(dp->mi->r4300);
}
void write_dpc_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -119,7 +118,15 @@ void write_dpc_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mas
unprotect_framebuffers(&dp->fb);
gfx.processRDPList();
protect_framebuffers(&dp->fb);
signal_rcp_interrupt(dp->mi, MI_INTR_DP);
if (dp->mi->regs[MI_INTR_REG] & MI_INTR_DP)
{
dp->mi->regs[MI_INTR_REG] &= ~MI_INTR_DP;
if (dp->dpc_regs[DPC_STATUS_REG] & DPC_STATUS_FREEZE) {
dp->do_on_unfreeze |= DELAY_DP_INT;
} else {
add_interrupt_event(&dp->mi->r4300->cp0, DP_INT, 8000);
}
}
break;
}
}
@@ -131,7 +138,6 @@ void read_dps_regs(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = dps_reg(address);
*value = dp->dps_regs[reg];
cp0_uncached_read(dp->mi->r4300);
}
void write_dps_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/ri/ri_controller.c
-1
View File
@@ -44,7 +44,6 @@ void read_ri_regs(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = ri_reg(address);
*value = ri->regs[reg];
cp0_uncached_read(ri->rdram->r4300);
}
void write_ri_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/rsp/rsp_core.c
+16 -30
View File
@@ -48,8 +48,6 @@ static void do_sp_dma(struct rsp_core* sp, const struct sp_dma* dma)
unsigned int memaddr = dma->memaddr & 0xff8;
unsigned int dramaddr = dma->dramaddr & 0xfffff8;
unsigned int initial_memaddr = memaddr;
unsigned int initial_dramaddr = dramaddr;
unsigned char *spmem = (unsigned char*)sp->mem + (dma->memaddr & 0x1000);
unsigned char *dram = (unsigned char*)sp->ri->rdram->dram;
@@ -61,10 +59,13 @@ static void do_sp_dma(struct rsp_core* sp, const struct sp_dma* dma)
dram[dramaddr^S8] = spmem[memaddr^S8];
memaddr++;
dramaddr++;
sp->regs[SP_MEM_ADDR_REG]++;
sp->regs[SP_DRAM_ADDR_REG]++;
}
post_framebuffer_write(&sp->dp->fb, dramaddr - length, length);
dramaddr+=skip;
sp->regs[SP_DRAM_ADDR_REG]+=skip;
}
}
else
@@ -76,12 +77,13 @@ static void do_sp_dma(struct rsp_core* sp, const struct sp_dma* dma)
spmem[memaddr^S8] = dram[dramaddr^S8];
memaddr++;
dramaddr++;
sp->regs[SP_MEM_ADDR_REG]++;
sp->regs[SP_DRAM_ADDR_REG]++;
}
dramaddr+=skip;
sp->regs[SP_DRAM_ADDR_REG]+=skip;
}
}
sp->regs[SP_MEM_ADDR_REG] += memaddr - initial_memaddr;
sp->regs[SP_DRAM_ADDR_REG] += dramaddr - initial_dramaddr;
/* schedule end of dma event */
add_interrupt_event(&sp->mi->r4300->cp0, RSP_DMA_EVT, ((count * length) / 10) + 4);
}
@@ -166,14 +168,8 @@ static void update_sp_status(struct rsp_core* sp, uint32_t w)
/* clear / set signal 0 */
if (w & 0x200) sp->regs[SP_STATUS_REG] &= ~SP_STATUS_SIG0;
if (w & 0x400)
{
sp->regs[SP_STATUS_REG] |= SP_STATUS_SIG0;
// This is a timing hack, some games seem to think the RSP should still be running after we've stopped it
// They set SP_STATUS_YIELD (SP_STATUS_SIG0), expecting the RSP to yield and generate an interrupt
if (sp->rsp_force_interrupt)
signal_rcp_interrupt(sp->mi, MI_INTR_SP);
}
if (w & 0x400) sp->regs[SP_STATUS_REG] |= SP_STATUS_SIG0;
/* clear / set signal 1 */
if (w & 0x800) sp->regs[SP_STATUS_REG] &= ~SP_STATUS_SIG1;
@@ -213,14 +209,12 @@ void init_rsp(struct rsp_core* sp,
uint32_t* sp_mem,
struct mi_controller* mi,
struct rdp_core* dp,
struct ri_controller* ri,
uint32_t rsp_force_interrupt)
struct ri_controller* ri)
{
sp->mem = sp_mem;
sp->mi = mi;
sp->dp = dp;
sp->ri = ri;
sp->rsp_force_interrupt = rsp_force_interrupt;
}
void poweron_rsp(struct rsp_core* sp)
@@ -231,7 +225,6 @@ void poweron_rsp(struct rsp_core* sp)
memset(sp->fifo, 0, SP_DMA_FIFO_SIZE*sizeof(struct sp_dma));
sp->rsp_status = 0;
sp->rsp_cycles = 0;
sp->mi->r4300->cp0.interrupt_unsafe_state &= ~(INTR_UNSAFE_RSP | INTR_UNSAFE_RSP_TASK);
sp->regs[SP_STATUS_REG] = 1;
}
@@ -243,7 +236,6 @@ void read_rsp_mem(void* opaque, uint32_t address, uint32_t* value)
uint32_t addr = rsp_mem_address(address);
*value = sp->mem[addr];
cp0_uncached_read(sp->mi->r4300);
}
void write_rsp_mem(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -266,7 +258,6 @@ void read_rsp_regs(void* opaque, uint32_t address, uint32_t* value)
{
sp->regs[SP_SEMAPHORE_REG] = 1;
}
cp0_uncached_read(sp->mi->r4300);
}
void write_rsp_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -305,7 +296,6 @@ void read_rsp_regs2(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = rsp_reg2(address);
*value = sp->regs2[reg];
cp0_uncached_read(sp->mi->r4300);
}
void write_rsp_regs2(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -322,18 +312,17 @@ void do_SP_Task(struct rsp_core* sp)
return;
uint32_t saved_status = sp->regs[SP_STATUS_REG];
uint32_t sp_delay_time = 0;
unprotect_framebuffers(&sp->dp->fb);
sp->rsp_cycles = (rsp.doRspCycles(0xffffffff) / 4) * 10;
uint32_t rsp_cycles = rsp.doRspCycles(0xffffffff) / 2;
if (sp->mi->regs[MI_INTR_REG] & MI_INTR_DP)
{
new_frame();
sp->mi->regs[MI_INTR_REG] &= ~MI_INTR_DP;
if (sp->dp->dpc_regs[DPC_STATUS_REG] & DPC_STATUS_FREEZE) {
sp->dp->do_on_unfreeze |= DELAY_DP_INT;
} else {
add_interrupt_event(&sp->mi->r4300->cp0, DP_INT, sp->rsp_cycles + 8000);
add_interrupt_event(&sp->mi->r4300->cp0, DP_INT, rsp_cycles + 2000);
}
}
protect_framebuffers(&sp->dp->fb);
@@ -341,24 +330,21 @@ void do_SP_Task(struct rsp_core* sp)
sp->rsp_status = sp->regs[SP_STATUS_REG];
if ((sp->regs[SP_STATUS_REG] & (SP_STATUS_HALT | SP_STATUS_BROKE)) == 0 && !get_event(&sp->mi->r4300->cp0.q, RSP_TSK_EVT))
{
sp_delay_time = 2000;
add_interrupt_event(&sp->mi->r4300->cp0, RSP_TSK_EVT, sp_delay_time);
add_interrupt_event(&sp->mi->r4300->cp0, RSP_TSK_EVT, 2000);
sp->mi->r4300->cp0.interrupt_unsafe_state |= INTR_UNSAFE_RSP_TASK;
}
if ((sp->regs[SP_STATUS_REG] & SP_STATUS_BROKE) && (sp->regs[SP_STATUS_REG] & SP_STATUS_INTR_BREAK))
{
sp_delay_time = sp->rsp_cycles & ~0xff;
add_interrupt_event(&sp->mi->r4300->cp0, SP_INT, sp_delay_time);
add_interrupt_event(&sp->mi->r4300->cp0, SP_INT, rsp_cycles);
sp->mi->r4300->cp0.interrupt_unsafe_state |= INTR_UNSAFE_RSP;
sp->regs[SP_STATUS_REG] = saved_status;
}
else if (sp->mi->regs[MI_INTR_REG] & MI_INTR_SP)
{
sp_delay_time = sp->rsp_cycles & ~0xff;
add_interrupt_event(&sp->mi->r4300->cp0, SP_INT, sp_delay_time);
add_interrupt_event(&sp->mi->r4300->cp0, SP_INT, rsp_cycles);
sp->mi->r4300->cp0.interrupt_unsafe_state |= INTR_UNSAFE_RSP;
sp->mi->regs[MI_INTR_REG] &= ~MI_INTR_SP;
}
sp->mi->regs[MI_INTR_REG] &= ~MI_INTR_SP;
}
void rsp_interrupt_event(void* opaque)
mupen64plus-core/src/device/rcp/rsp/rsp_core.h
+1 -4
View File
@@ -97,8 +97,6 @@ struct rsp_core
uint32_t regs[SP_REGS_COUNT];
uint32_t regs2[SP_REGS2_COUNT];
uint32_t rsp_status;
uint32_t rsp_cycles;
uint32_t rsp_force_interrupt;
struct mi_controller* mi;
struct rdp_core* dp;
@@ -125,8 +123,7 @@ void init_rsp(struct rsp_core* sp,
uint32_t* sp_mem,
struct mi_controller* mi,
struct rdp_core* dp,
struct ri_controller* ri,
uint32_t rsp_force_interrupt);
struct ri_controller* ri);
void poweron_rsp(struct rsp_core* sp);
mupen64plus-core/src/device/rcp/si/si_controller.c
+1 -2
View File
@@ -69,7 +69,7 @@ static void copy_pif_rdram(struct si_controller* si)
dram[i] = tohl(pif_ram[i]);
}
}
si->regs[SI_DRAM_ADDR_REG] += (PIF_RAM_SIZE / 4);
si->regs[SI_DRAM_ADDR_REG] += PIF_RAM_SIZE;
}
static void dma_si_write(struct si_controller* si)
@@ -122,7 +122,6 @@ void read_si_regs(void* opaque, uint32_t address, uint32_t* value)
uint32_t reg = si_reg(address);
*value = si->regs[reg];
cp0_uncached_read(si->mi->r4300);
}
void write_si_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rcp/vi/vi_controller.c
-1
View File
@@ -104,7 +104,6 @@ void read_vi_regs(void* opaque, uint32_t address, uint32_t* value)
}
*value = vi->regs[reg];
cp0_uncached_read(vi->mi->r4300);
}
void write_vi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/device/rdram/rdram.c
+1 -4
View File
@@ -100,7 +100,6 @@ static void read_rdram_dram_corrupted(void* opaque, uint32_t address, uint32_t*
if ((mode & 0x80000000) && (cc_value(mode) == 0)) {
*value = 0;
}
cp0_uncached_read(rdram->r4300);
}
static void map_corrupt_rdram(struct rdram* rdram, int corrupt)
@@ -180,7 +179,6 @@ void read_rdram_regs(void* opaque, uint32_t address, uint32_t* value)
if (reg == RDRAM_MODE_REG) {
*value ^= UINT32_C(0xc0c0c0c0);
}
cp0_uncached_read(rdram->r4300);
}
void write_rdram_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
@@ -227,14 +225,13 @@ void write_rdram_regs(void* opaque, uint32_t address, uint32_t value, uint32_t m
}
}
void read_rdram_dram(void* opaque, uint32_t address, uint32_t* value)
{
struct rdram* rdram = (struct rdram*)opaque;
uint32_t addr = rdram_dram_address(address);
*value = rdram->dram[addr];
cp0_uncached_read(rdram->r4300);
cp0_dcm_interlock(rdram->r4300, 11);
}
void write_rdram_dram(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
mupen64plus-core/src/main/main.c
+2 -5
View File
@@ -837,7 +837,7 @@ static void video_plugin_render_callback(int bScreenRedrawn)
}
}
void new_frame(void)
static void new_frame(void)
{
if (g_FrameCallback != NULL)
(*g_FrameCallback)(l_CurrentFrame);
@@ -956,6 +956,7 @@ static void pause_loop(void)
* Allow the core to perform various things */
void new_vi(void)
{
new_frame();
#if defined(PROFILE)
timed_sections_refresh();
#endif
@@ -1480,7 +1481,6 @@ m64p_error main_run(void)
struct file_storage sra;
size_t dd_rom_size;
struct dd_disk dd_disk;
uint32_t rsp_force_interrupt;
int control_ids[GAME_CONTROLLERS_COUNT];
struct controller_input_compat cin_compats[GAME_CONTROLLERS_COUNT];
@@ -1518,8 +1518,6 @@ m64p_error main_run(void)
//We disable any randomness for netplay
randomize_interrupt = !netplay_is_init() ? ConfigGetParamBool(g_CoreConfig, "RandomizeInterrupt") : 0;
rsp_force_interrupt = ROM_SETTINGS.rspforceinterrupt;
if (ROM_SETTINGS.disableextramem)
disable_extra_mem = ROM_SETTINGS.disableextramem;
else
@@ -1777,7 +1775,6 @@ m64p_error main_run(void)
no_compiled_jump,
randomize_interrupt,
g_start_address,
rsp_force_interrupt,
&g_dev.ai, &g_iaudio_out_backend_plugin_compat,
rdram_size,
joybus_devices, ijoybus_devices,
mupen64plus-core/src/main/main.h
-1
View File
@@ -58,7 +58,6 @@ extern int g_gs_vi_counter;
const char* get_savestatepath(void);
const char* get_savesrampath(void);
void new_frame(void);
void new_vi(void);
void main_switch_next_pak(int control_id);
mupen64plus-core/src/main/rom.c
-14
View File
@@ -179,7 +179,6 @@ m64p_error open_rom(const unsigned char* romimage, unsigned int size)
ROM_SETTINGS.mempak = entry->mempak;
ROM_SETTINGS.biopak = entry->biopak;
ROM_SETTINGS.disableextramem = entry->disableextramem;
ROM_SETTINGS.rspforceinterrupt = entry->rspforceinterrupt;
ROM_PARAMS.cheats = entry->cheats;
}
else
@@ -195,7 +194,6 @@ m64p_error open_rom(const unsigned char* romimage, unsigned int size)
ROM_SETTINGS.mempak = 1;
ROM_SETTINGS.biopak = 0;
ROM_SETTINGS.disableextramem = DEFAULT_DISABLE_EXTRA_MEM;
ROM_SETTINGS.rspforceinterrupt = DEFAULT_RSP_FORCE_INTERRUPT;
ROM_PARAMS.cheats = NULL;
}
@@ -334,12 +332,6 @@ static size_t romdatabase_resolve_round(void)
entry->entry.set_flags |= ROMDATABASE_ENTRY_EXTRAMEM;
}
if (!isset_bitmask(entry->entry.set_flags, ROMDATABASE_ENTRY_RSPFORCEINTERRUPT) &&
isset_bitmask(ref->set_flags, ROMDATABASE_ENTRY_RSPFORCEINTERRUPT)) {
entry->entry.rspforceinterrupt = ref->rspforceinterrupt;
entry->entry.set_flags |= ROMDATABASE_ENTRY_RSPFORCEINTERRUPT;
}
if (!isset_bitmask(entry->entry.set_flags, ROMDATABASE_ENTRY_TRANSFERPAK) &&
isset_bitmask(ref->set_flags, ROMDATABASE_ENTRY_TRANSFERPAK)) {
entry->entry.transferpak = ref->transferpak;
@@ -448,7 +440,6 @@ void romdatabase_open(void)
search->entry.players = 4;
search->entry.rumble = 1;
search->entry.disableextramem = DEFAULT_DISABLE_EXTRA_MEM;
search->entry.rspforceinterrupt = DEFAULT_RSP_FORCE_INTERRUPT;
search->entry.cheats = NULL;
search->entry.transferpak = 0;
search->entry.mempak = 1;
@@ -565,11 +556,6 @@ void romdatabase_open(void)
search->entry.disableextramem = atoi(l.value);
search->entry.set_flags |= ROMDATABASE_ENTRY_EXTRAMEM;
}
else if (!strcmp(l.name, "RspForceInterrupt"))
{
search->entry.rspforceinterrupt = atoi(l.value);
search->entry.set_flags |= ROMDATABASE_ENTRY_RSPFORCEINTERRUPT;
}
else if(!strncmp(l.name, "Cheat", 5))
{
size_t len1 = 0, len2 = 0;
mupen64plus-core/src/main/rom.h
-4
View File
@@ -108,7 +108,6 @@ typedef struct
unsigned char players; /* Local players 0-4, 2/3/4 way Netplay indicated by 5/6/7. */
unsigned char rumble; /* 0 - No, 1 - Yes boolean for rumble support. */
unsigned char disableextramem;
unsigned char rspforceinterrupt;
unsigned char transferpak; /* 0 - No, 1 - Yes boolean for transferpak support. */
unsigned char mempak; /* 0 - No, 1 - Yes boolean for mempak support. */
unsigned char biopak; /* 0 - No, 1 - Yes boolean for biopak support. */
@@ -127,12 +126,9 @@ typedef struct
#define ROMDATABASE_ENTRY_TRANSFERPAK BIT(9)
#define ROMDATABASE_ENTRY_MEMPAK BIT(10)
#define ROMDATABASE_ENTRY_BIOPAK BIT(11)
#define ROMDATABASE_ENTRY_RSPFORCEINTERRUPT BIT(14)
/* by default, extra mem is enabled */
enum { DEFAULT_DISABLE_EXTRA_MEM = 0 };
/* Default RSP Force Interrupt */
enum { DEFAULT_RSP_FORCE_INTERRUPT = 0 };
typedef struct _romdatabase_search
{