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update core
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@@ -169,6 +169,7 @@ void read_cart_dom2(void* opaque, uint32_t address, uint32_t* value)
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cart->use_flashram = 1;
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read_flashram(&cart->flashram, address, value);
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}
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cp0_rom_interlock(cart->cart_rom.r4300, pi_calculate_cycles(cart->cart_rom.pi, 2, 4));
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}
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void write_cart_dom2(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
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@@ -190,6 +191,9 @@ void write_cart_dom2(void* opaque, uint32_t address, uint32_t value, uint32_t ma
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cart->use_flashram = 1;
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write_flashram(&cart->flashram, address, value, mask);
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}
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/* Mark IO as busy */
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cart->cart_rom.pi->regs[PI_STATUS_REG] |= PI_STATUS_IO_BUSY;
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add_interrupt_event(&cart->cart_rom.r4300->cp0, PI_INT, pi_calculate_cycles(cart->cart_rom.pi, 2, 4) / 2);
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}
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uint32_t cart_dom2_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
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@@ -547,7 +547,11 @@ void read_dd_rom(void* opaque, uint32_t address, uint32_t* value)
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void write_dd_rom(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
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{
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struct dd_controller* dd = (struct dd_controller*)opaque;
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DebugMessage(M64MSG_VERBOSE, "DD ROM: %08X <- %08x & %08x", address, value, mask);
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/* Mark IO as busy */
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dd->pi->regs[PI_STATUS_REG] |= PI_STATUS_IO_BUSY;
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add_interrupt_event(&dd->r4300->cp0, PI_INT, pi_calculate_cycles(dd->pi, 1, 4) / 2);
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}
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uint32_t dd_dom_dma_read(void* opaque, const uint8_t* dram, uint32_t dram_addr, uint32_t cart_addr, uint32_t length)
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