Unknown W. Brackets 7b081a61c8 irjit: Correct another PurgeTemps case. ...

In this case:
  Mov A, B
  AndConst A, A, 1
  Load32 C, A, 0

Was still swapping the Load32 to B, not just the AndConst.

Fixes #15735.

2022-07-27 19:38:16 -07:00

..

IRAsm.cpp

Remove most instances of base/logging.h from Common, Core, GPU, more

2020-08-15 19:08:44 +02:00

IRCompALU.cpp

Common: Maintain C++11 support in sign extend.

2021-01-31 08:44:02 -08:00

IRCompBranch.cpp

jit: Count delay slot cycles separately.

2021-04-12 07:04:22 -07:00

IRCompFPU.cpp

jit: Fix conditional disable flags.

2021-01-09 11:50:32 -08:00

IRCompLoadStore.cpp

jit: Fix conditional disable flags.

2021-01-09 11:50:32 -08:00

IRCompVFPU.cpp

Global: Remove some unused variables.

2021-02-15 11:59:45 -08:00

IRFrontend.cpp

Remove most instances of base/logging.h from Common, Core, GPU, more

2020-08-15 19:08:44 +02:00

IRFrontend.h

Minor cleanup

2018-01-10 09:19:27 +01:00

IRInst.cpp

irjit: Fix mtv for INF4.

2021-01-09 12:43:50 -08:00

IRInst.h

jit: Avoid using mips identifier directly.

2021-02-26 07:24:58 -08:00

IRInterpreter.cpp

Add ARM64_NEON compile arch flag

2022-06-25 07:29:20 +02:00

IRInterpreter.h

jit: Avoid using mips identifier directly.

2021-02-26 07:24:58 -08:00

IRJit.cpp

irjit: Allow unaligned loads by default.

2022-07-11 17:36:39 -07:00

IRJit.h

Global: Reduce includes of common headers.

2022-01-30 16:35:33 -08:00

IRPassSimplify.cpp

irjit: Correct another PurgeTemps case.

2022-07-27 19:38:16 -07:00

IRPassSimplify.h

irjit: Combine lwl/lwr and swl/swr, like before.

2018-01-07 21:05:58 -08:00

IRRegCache.cpp

irjit: Add tests for IR passes.

2022-07-24 11:35:54 -07:00

IRRegCache.h

jit-ir: Less instructions cause flushing in constant propagation.

2016-05-08 23:25:08 +02:00