mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
6d105ae35d
The backend follows the ARM64 one: a dispatcher, a register cache on top of the IR one, and native exits, syscalls, breakpoints and transfers. Everything else goes to the IR interpreter for now. Floats are mapped one lane per S register (no SIMD mapping yet), and addresses are masked, as on every 32-bit build. The JIT core now uses it on ARM32 in place of the old ArmJit. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
135 lines
3.4 KiB
C++
135 lines
3.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Core/MIPS/ARM/ArmIRJit.h"
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#include "Core/MIPS/ARM/ArmIRRegCache.h"
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// This file contains compilation for exits.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace ArmGen;
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using namespace ArmIRJitConstants;
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void ArmJitBackend::CompIR_Exit(IRInst inst) {
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CONDITIONAL_DISABLE;
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ARMReg exitReg = INVALID_REG;
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switch (inst.op) {
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case IROp::ExitToConst:
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FlushAll();
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WriteConstExit(inst.constant);
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break;
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case IROp::ExitToReg:
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exitReg = regs_.MapGPR(inst.src1);
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FlushAll();
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MOV(SCRATCH1, exitReg);
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B(dispatcherPCInSCRATCH1_);
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break;
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case IROp::ExitToPC:
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FlushAll();
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B(dispatcherCheckCoreState_);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_ExitIf(IRInst inst) {
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CONDITIONAL_DISABLE;
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ARMReg lhs = INVALID_REG;
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ARMReg rhs = INVALID_REG;
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FixupBranch fixup;
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switch (inst.op) {
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case IROp::ExitToConstIfEq:
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case IROp::ExitToConstIfNeq:
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if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {
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lhs = regs_.MapGPR(inst.src2);
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FlushAll();
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CMP(lhs, Operand2(0));
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} else if (regs_.IsGPRImm(inst.src2) && regs_.GetGPRImm(inst.src2) == 0) {
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lhs = regs_.MapGPR(inst.src1);
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FlushAll();
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CMP(lhs, Operand2(0));
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} else {
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regs_.Map(inst);
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lhs = regs_.R(inst.src1);
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rhs = regs_.R(inst.src2);
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FlushAll();
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CMP(lhs, rhs);
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}
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fixup = B_CC(inst.op == IROp::ExitToConstIfEq ? CC_NEQ : CC_EQ);
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WriteConstExit(inst.constant);
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SetJumpTarget(fixup);
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break;
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case IROp::ExitToConstIfGtZ:
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case IROp::ExitToConstIfGeZ:
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case IROp::ExitToConstIfLtZ:
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case IROp::ExitToConstIfLeZ:
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{
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lhs = regs_.MapGPR(inst.src1);
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FlushAll();
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CMP(lhs, Operand2(0));
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// Branch over the exit when the condition fails.
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CCFlags skip = CC_AL;
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switch (inst.op) {
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case IROp::ExitToConstIfGtZ: skip = CC_LE; break;
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case IROp::ExitToConstIfGeZ: skip = CC_LT; break;
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case IROp::ExitToConstIfLtZ: skip = CC_GE; break;
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case IROp::ExitToConstIfLeZ: skip = CC_GT; break;
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default: break;
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}
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fixup = B_CC(skip);
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WriteConstExit(inst.constant);
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SetJumpTarget(fixup);
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break;
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}
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case IROp::ExitToConstIfFpTrue:
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case IROp::ExitToConstIfFpFalse:
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// Note: not used.
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DISABLE;
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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