Henrik Rydgård a7bc70834c Merge pull request #17907 from unknownbrackets/riscv-minor ...

riscv: Implement vs2i

2023-08-14 07:41:45 +02:00

..

RiscVAsm.cpp

riscv: Reduce call bloat using temps.

2023-08-08 23:17:32 -07:00

RiscVCompALU.cpp

riscv: Implement ReverseBits in jit.

2023-08-08 23:17:32 -07:00

RiscVCompBranch.cpp

riscv: Enable block linking.

2023-08-12 09:37:02 -07:00

RiscVCompFPU.cpp

riscv: Remove FMul safety check.

2023-08-13 10:20:20 -07:00

RiscVCompLoadStore.cpp

riscv: Fix load error w/o pointerify.

2023-08-13 10:20:28 -07:00

RiscVCompSystem.cpp

irjit: ZeroFpCond -> FpCondFromReg.

2023-08-13 10:40:47 -07:00

RiscVCompVec.cpp

riscv: Implement vs2i.

2023-08-13 18:27:19 -07:00

RiscVJit.cpp

riscv: Switch to the logBlocks model for disasm.

2023-08-13 10:37:21 -07:00

RiscVJit.h

riscv: Switch to the logBlocks model for disasm.

2023-08-13 10:37:21 -07:00

RiscVRegCache.cpp

Merge pull request #17815 from unknownbrackets/riscv-jit

2023-07-30 14:49:37 -07:00

RiscVRegCache.h

riscv: Spill registers more intelligently.

2023-07-30 14:24:12 -07:00

RiscVRegCacheFPU.cpp

riscv: Make Vec4Shuffle overlap safe.

2023-08-08 23:00:45 -07:00

RiscVRegCacheFPU.h

riscv: Make Vec4Shuffle overlap safe.

2023-08-08 23:00:45 -07:00