Henrik Rydgård 9fffa33eee Merge pull request #18234 from unknownbrackets/x86-ir-transfer ...

x86jit: Perform vector transfers instead of flushing to memory

2023-09-26 09:28:05 +02:00

..

RiscVAsm.cpp

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVCompALU.cpp

riscv: Use a single reg for LO/HI.

2023-08-20 14:49:09 -07:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVCompVec.cpp

arm64jit: Implement Vec4Blend.

2023-09-05 00:10:26 -07:00

RiscVJit.cpp

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVJit.h

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVRegCache.cpp

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00