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MeCore owns a second MIPSState in the ME's address space, held in reset until released (SetReset). It runs on the interpreter, a slice behind the main CPU: CoreTiming runs it for the cycles the main CPU has just used, in Advance and ForceCheck. Its own PRId (COP0 22) and mfic/mtic flag; MMIO counts as kernel mode on it, and a syscall stops it with an error rather than reaching HLE. The interpreter's block stepping reads delay slots through the stepping CPU's memory, and cache instructions log at verbose level, as ME code flushes its caches in a loop. Created at boot only for homebrew (PBP with MG category or no SFO, ELF; the VSH counts, as vshmain.prx loads as an ELF), when "Enable ME emulation for homebrew" is on: a global checkbox in developer settings, off by default and not translated yet, or --me-core. Saved in its own section after MMIO (SaveStart v5), with its own memory; loading a state creates or removes the ME to match. The boot page now starts with a reset stub that sends the ME on to 0xBFC00040, where homebrew puts its code (from the firmware's reset code, read on a PSP-1000). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
145 lines
4.4 KiB
C++
145 lines
4.4 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include <cstring>
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#include <vector>
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#include "Common/Log.h"
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#include "Common/Serialize/Serializer.h"
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#include "Common/Serialize/SerializeFuncs.h"
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#include "Core/HW/GpioMMIO.h"
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#include "Core/HW/MMIO.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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namespace MMIO {
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// The boot page (see Memory::GetBootPage) is RAM, which the main CPU reaches through here.
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class BootPageDevice : public MMIODevice {
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public:
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BootPageDevice() : MMIODevice("boot page", Memory::BOOT_PAGE_ADDRESS, Memory::BOOT_PAGE_SIZE) {}
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bool Read(MIPSState *mips, u32 offset, int size, u32 *value) override {
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if (offset + size > Memory::BOOT_PAGE_SIZE)
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return false;
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const u8 *ptr = Memory::GetBootPage() + offset;
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switch (size) {
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case 1: *value = *ptr; break;
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case 2: *value = *(const u16_le *)ptr; break;
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default: *value = *(const u32_le *)ptr; break;
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}
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return true;
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}
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bool Write(MIPSState *mips, u32 offset, int size, u32 value) override {
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if (offset + size > Memory::BOOT_PAGE_SIZE)
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return false;
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u8 *ptr = Memory::GetBootPage() + offset;
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switch (size) {
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case 1: *ptr = (u8)value; break;
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case 2: *(u16_le *)ptr = (u16)value; break;
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default: *(u32_le *)ptr = value; break;
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}
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// The ME runs code from here, uncached, so it sees new code at once (MIST patches the
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// bootstrap, me/vram puts it back after its own stub). Reaches the ME's JIT too.
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if (mips)
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mips->InvalidateICacheRangeDeferred(Memory::BOOT_PAGE_ADDRESS + offset, size);
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return true;
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}
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// Both CPUs reset to the start of the page. The firmware leaves code there that sends the ME
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// (whose COP0 register 22 is nonzero) on to 0x40, where homebrew puts its ME code (read on a
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// PSP-1000 under PSPLink). The main CPU's half isn't needed, it never resets under HLE.
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void Reset() override {
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u8 *page = Memory::GetBootPage();
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memset(page, 0, Memory::BOOT_PAGE_SIZE);
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const u32 code[] = {
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0x4002B000, // mfc0 v0, $22
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0x1440000E, // bnez v0, 0xBFC00040
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0x00000000, // nop
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0x1000FFFF, // b .
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0x00000000, // nop
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};
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for (size_t i = 0; i < ARRAY_SIZE(code); ++i) {
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((u32_le *)page)[i] = code[i];
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}
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}
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void DoState(PointerWrap &p) override {
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DoArray(p, Memory::GetBootPage(), Memory::BOOT_PAGE_SIZE);
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}
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};
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static BootPageDevice g_bootPage;
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static std::vector<MMIODevice *> g_devices;
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void Init() {
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g_devices = {
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GpioMMIO::Device(),
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SysconSerialMMIO::Device(),
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&g_bootPage,
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};
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for (MMIODevice *device : g_devices) {
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device->Reset();
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}
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}
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void Shutdown() {
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g_devices.clear();
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}
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void DoState(PointerWrap &p) {
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auto s = p.Section("MMIO", 1, 2);
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if (!s)
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return;
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// Every device, whether or not this boot registered it, so the layout doesn't depend on that.
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GpioMMIO::Device()->DoState(p);
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SysconSerialMMIO::Device()->DoState(p);
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if (s >= 2) {
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g_bootPage.DoState(p);
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} else if (p.mode == PointerWrap::MODE_READ) {
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g_bootPage.Reset();
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}
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}
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static MMIODevice *FindDevice(u32 address) {
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for (MMIODevice *device : g_devices) {
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if (device->Contains(address))
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return device;
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}
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return nullptr;
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}
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u32 Read(MIPSState *mips, u32 address, int size) {
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MMIODevice *device = FindDevice(address);
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u32 value;
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if (device && device->Read(mips, address - device->Base(), size, &value))
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return value;
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WARN_LOG(Log::CPU, "Unhandled MMIO Read%d at %08x%s%s", size * 8, address, device ? " in " : "", device ? device->Name() : "");
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return UNHANDLED_READ;
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}
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void Write(MIPSState *mips, u32 address, int size, u32 value) {
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MMIODevice *device = FindDevice(address);
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if (device && device->Write(mips, address - device->Base(), size, value))
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return;
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WARN_LOG(Log::CPU, "Unhandled MMIO Write%d at %08x = %08x%s%s", size * 8, address, value, device ? " in " : "", device ? device->Name() : "");
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}
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} // namespace MMIO
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