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Unknown W. Brackets
ab809bd19e
Otherwise, the block will be executed with the wrong rounding mode the first time rounding is set. This could be important if it was set for a single operation. This is only a problem the first time it's set.
411 lines
11 KiB
C++
411 lines
11 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM64)
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#include "Core/Config.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/ARM64/Arm64Jit.h"
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#include "Core/MIPS/ARM64/Arm64RegCache.h"
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#include "Common/CPUDetect.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// FPCR interesting bits:
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// 24: FZ (flush-to-zero)
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// 23:22: RMode (0 = nearest, 1 = +inf, 2 = -inf, 3 = zero)
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// not much else is interesting for us, but should be preserved.
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// To access: MRS Xt, FPCR ; MSR FPCR, Xt
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE ;
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#define DISABLE { Comp_Generic(op); return; }
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namespace MIPSComp {
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using namespace Arm64Gen;
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using namespace Arm64JitConstants;
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void Arm64Jit::Comp_FPU3op(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int ft = _FT;
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int fs = _FS;
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int fd = _FD;
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fpr.MapDirtyInIn(fd, fs, ft);
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switch (op & 0x3f) {
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case 0: fp.FADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
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case 1: fp.FSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: fp.FMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) * F(ft); //mul
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case 3: fp.FDIV(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) / F(ft); //div
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default:
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DISABLE;
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return;
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}
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}
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void Arm64Jit::Comp_FPULS(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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// Surprisingly, these work fine alraedy.
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s32 offset = (s16)(op & 0xFFFF);
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int ft = _FT;
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MIPSGPReg rs = _RS;
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// u32 addr = R(rs) + offset;
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// logBlocks = 1;
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std::vector<FixupBranch> skips;
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switch (op >> 26) {
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case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
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if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset <= 16380 && offset >= 0) {
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gpr.MapRegAsPointer(rs);
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fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
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fp.LDR(32, INDEX_UNSIGNED, fpr.R(ft), gpr.RPtr(rs), offset);
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break;
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}
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fpr.SpillLock(ft);
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fpr.MapReg(ft, MAP_NOINIT | MAP_DIRTY);
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if (gpr.IsImm(rs)) {
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u32 addr = offset + gpr.GetImm(rs);
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gpr.SetRegImm(SCRATCH1, addr);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetScratch1ToEffectiveAddress(rs, offset);
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} else {
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skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
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}
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}
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fp.LDR(32, fpr.R(ft), SCRATCH1_64, ArithOption(MEMBASEREG));
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for (auto skip : skips) {
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SetJumpTarget(skip);
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}
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fpr.ReleaseSpillLocksAndDiscardTemps();
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break;
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case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
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if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset <= 16380 && offset >= 0) {
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gpr.MapRegAsPointer(rs);
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fpr.MapReg(ft, 0);
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fp.STR(32, INDEX_UNSIGNED, fpr.R(ft), gpr.RPtr(rs), offset);
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break;
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}
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fpr.MapReg(ft);
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if (gpr.IsImm(rs)) {
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u32 addr = offset + gpr.GetImm(rs);
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gpr.SetRegImm(SCRATCH1, addr);
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} else {
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gpr.MapReg(rs);
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if (g_Config.bFastMemory) {
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SetScratch1ToEffectiveAddress(rs, offset);
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} else {
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skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2);
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}
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}
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fp.STR(32, fpr.R(ft), SCRATCH1_64, ArithOption(MEMBASEREG));
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for (auto skip : skips) {
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SetJumpTarget(skip);
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}
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Arm64Jit::Comp_FPUComp(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int opc = op & 0xF;
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if (opc >= 8) opc -= 8; // alias
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if (opc == 0) { // f, sf (signalling false)
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gpr.SetImm(MIPS_REG_FPCOND, 0);
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return;
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}
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int fs = _FS;
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int ft = _FT;
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gpr.MapReg(MIPS_REG_FPCOND, MAP_DIRTY | MAP_NOINIT);
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fpr.MapInIn(fs, ft);
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fp.FCMP(fpr.R(fs), fpr.R(ft));
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switch (opc) {
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case 1: // un, ngle (unordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_VS);
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break;
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case 2: // eq, seq (equal, ordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_EQ);
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break;
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case 3: // ueq, ngl (equal, unordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_EQ);
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// If ordered, use the above result. If unordered, use ZR+1 (being 1.)
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CSINC(gpr.R(MIPS_REG_FPCOND), gpr.R(MIPS_REG_FPCOND), WZR, CC_VC);
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return;
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case 4: // olt, lt (less than, ordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_LO);
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break;
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case 5: // ult, nge (less than, unordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_LT);
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break;
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case 6: // ole, le (less equal, ordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_LS);
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break;
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case 7: // ule, ngt (less equal, unordered)
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CSET(gpr.R(MIPS_REG_FPCOND), CC_LE);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Arm64Jit::Comp_FPU2op(MIPSOpcode op) {
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CONDITIONAL_DISABLE;
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int fs = _FS;
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int fd = _FD;
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switch (op & 0x3f) {
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case 4: //F(fd) = sqrtf(F(fs)); break; //sqrt
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fpr.MapDirtyIn(fd, fs);
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fp.FSQRT(fpr.R(fd), fpr.R(fs));
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break;
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case 5: //F(fd) = fabsf(F(fs)); break; //abs
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fpr.MapDirtyIn(fd, fs);
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fp.FABS(fpr.R(fd), fpr.R(fs));
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break;
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case 6: //F(fd) = F(fs); break; //mov
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fpr.MapDirtyIn(fd, fs);
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fp.FMOV(fpr.R(fd), fpr.R(fs));
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break;
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case 7: //F(fd) = -F(fs); break; //neg
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fpr.MapDirtyIn(fd, fs);
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fp.FNEG(fpr.R(fd), fpr.R(fs));
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break;
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case 12: //FsI(fd) = (int)floorf(F(fs)+0.5f); break; //round.w.s
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{
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fpr.MapDirtyIn(fd, fs);
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fp.FCMP(fpr.R(fs), fpr.R(fs)); // Detect NaN
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fp.FCVTS(fpr.R(fd), fpr.R(fs), ROUND_N); // to nearest, ties to even
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FixupBranch skip = B(CC_VC);
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MOVI2R(SCRATCH1, 0x7FFFFFFF);
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fp.FMOV(fpr.R(fd), SCRATCH1);
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SetJumpTarget(skip);
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break;
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}
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case 13: //FsI(fd) = Rto0(F(fs))); break; //trunc.w.s
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{
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fpr.MapDirtyIn(fd, fs);
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fp.FCMP(fpr.R(fs), fpr.R(fs));
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fp.FCVTS(fpr.R(fd), fpr.R(fs), ROUND_Z);
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FixupBranch skip = B(CC_VC);
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MOVI2R(SCRATCH1, 0x7FFFFFFF);
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fp.FMOV(fpr.R(fd), SCRATCH1);
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SetJumpTarget(skip);
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break;
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}
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case 14://FsI(fd) = (int)ceilf (F(fs)); break; //ceil.w.s
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{
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fpr.MapDirtyIn(fd, fs);
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fp.FCMP(fpr.R(fs), fpr.R(fs));
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fp.FCVTS(fpr.R(fd), fpr.R(fs), ROUND_P); // towards +inf
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FixupBranch skip = B(CC_VC);
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MOVI2R(SCRATCH1, 0x7FFFFFFF);
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fp.FMOV(fpr.R(fd), SCRATCH1);
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SetJumpTarget(skip);
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break;
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}
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case 15: //FsI(fd) = (int)floorf(F(fs)); break; //floor.w.s
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{
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fpr.MapDirtyIn(fd, fs);
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fp.FCMP(fpr.R(fs), fpr.R(fs));
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fp.FCVTS(fpr.R(fd), fpr.R(fs), ROUND_M); // towards -inf
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FixupBranch skip = B(CC_VC);
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MOVI2R(SCRATCH1, 0x7FFFFFFF);
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fp.FMOV(fpr.R(fd), SCRATCH1);
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SetJumpTarget(skip);
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break;
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}
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case 32: //F(fd) = (float)FsI(fs); break; //cvt.s.w
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fpr.MapDirtyIn(fd, fs);
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fp.SCVTF(fpr.R(fd), fpr.R(fs));
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break;
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case 36: //FsI(fd) = (int) F(fs); break; //cvt.w.s
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fpr.MapDirtyIn(fd, fs);
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if (js.hasSetRounding) {
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// We're just going to defer to our cached func. Here's the arg.
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fp.FMOV(S0, fpr.R(fs));
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MOVP2R(SCRATCH1_64, &js.currentRoundingFunc);
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LDR(INDEX_UNSIGNED, SCRATCH1_64, SCRATCH1_64, 0);
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BLR(SCRATCH1_64);
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fp.FMOV(fpr.R(fd), S0);
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} else {
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fp.FCMP(fpr.R(fs), fpr.R(fs));
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fp.FCVTS(fpr.R(fd), fpr.R(fs), ROUND_Z);
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FixupBranch skip_nan = B(CC_VC);
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MOVI2R(SCRATCH1, 0x7FFFFFFF);
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fp.FMOV(fpr.R(fd), SCRATCH1);
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SetJumpTarget(skip_nan);
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}
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break;
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default:
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DISABLE;
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}
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}
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void Arm64Jit::Comp_mxc1(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE;
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int fs = _FS;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f) {
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case 0: // R(rt) = FI(fs); break; //mfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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if (fpr.IsMapped(fs)) {
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fp.FMOV(gpr.R(rt), fpr.R(fs));
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} else {
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LDR(INDEX_UNSIGNED, gpr.R(rt), CTXREG, fpr.GetMipsRegOffset(fs));
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}
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return;
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case 2: //cfc1
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if (rt == MIPS_REG_ZERO) {
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return;
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}
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if (fs == 31) {
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if (gpr.IsImm(MIPS_REG_FPCOND)) {
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LDR(INDEX_UNSIGNED, gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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if (gpr.GetImm(MIPS_REG_FPCOND) & 1) {
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ORRI2R(gpr.R(rt), gpr.R(rt), 0x1 << 23, SCRATCH2);
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} else {
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ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), SCRATCH2);
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}
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} else {
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gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
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LDR(INDEX_UNSIGNED, gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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BFI(gpr.R(rt), gpr.R(MIPS_REG_FPCOND), 23, 1);
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}
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} else if (fs == 0) {
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gpr.SetImm(rt, MIPSState::FCR0_VALUE);
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} else {
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// Unsupported regs are always 0.
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gpr.SetImm(rt, 0);
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}
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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if (gpr.IsImm(rt)) {
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// This can't be run on LO/HI.
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uint32_t ival = (uint32_t)gpr.GetImm(rt);
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float floatval;
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memcpy(&floatval, &ival, sizeof(floatval));
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uint8_t imm8;
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// If zero, just zero it.
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fpr.MapReg(fs, MAP_NOINIT | MAP_DIRTY);
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if (ival == 0) {
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fp.FMOV(fpr.R(fs), WZR); // This is supposedly special cased in hardware to be fast.
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} else if (FPImm8FromFloat(floatval, &imm8)) {
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fp.FMOV(fpr.R(fs), imm8);
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} else {
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// Materialize the register and do a cross move.
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gpr.MapReg(rt);
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fp.FMOV(fpr.R(fs), gpr.R(rt));
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}
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} else {
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gpr.MapReg(rt);
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fpr.MapReg(fs, MAP_NOINIT | MAP_DIRTY);
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fp.FMOV(fpr.R(fs), gpr.R(rt));
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}
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return;
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case 6: //ctc1
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if (fs == 31) {
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// Must clear before setting, since ApplyRoundingMode() assumes it was cleared.
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RestoreRoundingMode();
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bool wasImm = gpr.IsImm(rt);
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u32 immVal = -1;
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if (wasImm) {
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immVal = gpr.GetImm(rt);
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gpr.SetImm(MIPS_REG_FPCOND, (immVal >> 23) & 1);
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gpr.MapReg(rt);
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} else {
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gpr.MapDirtyIn(MIPS_REG_FPCOND, rt);
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}
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// Update MIPS state
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// TODO: Technically, should mask by 0x0181FFFF. Maybe just put all of FCR31 in the reg?
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STR(INDEX_UNSIGNED, gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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if (!wasImm) {
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UBFX(gpr.R(MIPS_REG_FPCOND), gpr.R(rt), 23, 1);
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// TODO: We do have the fcr31 value in a register here, could use that in UpdateRoundingMode to avoid reloading it.
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UpdateRoundingMode();
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} else {
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UpdateRoundingMode(immVal);
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}
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ApplyRoundingMode();
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} else {
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Comp_Generic(op);
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}
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return;
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default:
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DISABLE;
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break;
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}
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}
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} // namespace MIPSComp
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#endif // PPSSPP_ARCH(ARM64)
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