Henrik RydgårdandClaude Opus 5.5 9a08ff39be VFPU: vmin and vmax order zeros and denormals as equal, on every core ...

On the PSP, zeros and denormals all compare equal, a tie returns the
second operand, and the result keeps its bits (cpu/vfpu/minmax_zero,
minmax_tie, fcr31). The interpreter got the ties and NaNs right but
compared denormals as numbers, and each JIT had its own fast path with
host min/max, which returned the first operand on a tie and flushed or
not depending on the host's mode.

All cores now compare by vfpu_minmax_key(), an integer key that is 0
for a zero exponent and orders the rest by sign and magnitude, and
select the operand by it, without branching on NaN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-14 11:59:35 +02:00

..

RiscVAsm.cpp

Keep JIT block entries and replacement hooks out of PSP memory

2026-10-11 10:33:30 +02:00

RiscVCompALU.cpp

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

VFPU: vmin and vmax order zeros and denormals as equal, on every core

2026-10-14 11:59:35 +02:00

RiscVCompLoadStore.cpp

IR native backends: Fix ll into $zero, and sc losing its result

2026-10-14 00:10:00 +02:00

RiscVCompSystem.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVCompVec.cpp

IR: Fold ClampToZero into the 31-bit packs

2026-09-24 14:31:22 -06:00

RiscVJit.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVJit.h

RISC-V JIT: Compile the bit ops and min/max without Zbb

2026-09-24 14:31:22 -06:00

RiscVRegCache.cpp

RISC-V IR: Allocate the saved registers before the temporaries

2026-09-24 16:22:41 -06:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00