mirror of
https://github.com/hrydgard/ppsspp.git
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352 lines
8.5 KiB
C++
352 lines
8.5 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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// In other words, PPSSPP_ARCH(ARM64) || DISASM_ALL.
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#if PPSSPP_ARCH(ARM64) || (PPSSPP_PLATFORM(WINDOWS) && !defined(__LIBRETRO__))
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#ifndef offsetof
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#include <cstddef>
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#endif
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#include "Core/MIPS/ARM64/Arm64IRJit.h"
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#include "Core/MIPS/ARM64/Arm64IRRegCache.h"
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// This file contains compilation for floating point related instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Arm64Gen;
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using namespace Arm64IRJitConstants;
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void Arm64JitBackend::CompIR_FArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::FAdd:
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regs_.Map(inst);
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fp_.FADD(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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case IROp::FSub:
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regs_.Map(inst);
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fp_.FSUB(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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case IROp::FMul:
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regs_.Map(inst);
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fp_.FMUL(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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case IROp::FDiv:
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regs_.Map(inst);
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fp_.FDIV(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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case IROp::FSqrt:
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regs_.Map(inst);
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fp_.FSQRT(regs_.F(inst.dest), regs_.F(inst.src1));
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break;
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case IROp::FNeg:
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regs_.Map(inst);
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fp_.FNEG(regs_.F(inst.dest), regs_.F(inst.src1));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::FMov:
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if (inst.dest != inst.src1) {
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regs_.Map(inst);
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fp_.FMOV(regs_.F(inst.dest), regs_.F(inst.src1));
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}
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break;
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case IROp::FAbs:
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regs_.Map(inst);
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fp_.FABS(regs_.F(inst.dest), regs_.F(inst.src1));
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break;
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case IROp::FSign:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FCompare(IRInst inst) {
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CONDITIONAL_DISABLE;
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constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC;
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switch (inst.op) {
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case IROp::FCmp:
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switch (inst.dest) {
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case IRFpCompareMode::False:
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regs_.SetGPRImm(IRREG_FPCOND, 0);
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break;
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case IRFpCompareMode::EitherUnordered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_VS);
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break;
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case IRFpCompareMode::EqualOrdered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_EQ);
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break;
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case IRFpCompareMode::EqualUnordered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_EQ);
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// If ordered, use the above result. If unordered, use ZR+1 (being 1.)
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CSINC(regs_.R(IRREG_FPCOND), regs_.R(IRREG_FPCOND), WZR, CC_VC);
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break;
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case IRFpCompareMode::LessEqualOrdered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_LS);
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break;
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case IRFpCompareMode::LessEqualUnordered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_LE);
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break;
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case IRFpCompareMode::LessOrdered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_LO);
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break;
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case IRFpCompareMode::LessUnordered:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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CSET(regs_.R(IRREG_FPCOND), CC_LT);
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break;
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default:
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_assert_msg_(false, "Unexpected IRFpCompareMode %d", inst.dest);
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}
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break;
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case IROp::FCmovVfpuCC:
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case IROp::FCmpVfpuBit:
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case IROp::FCmpVfpuAggregate:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FCondAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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// For Vec4, we could basically just ORR FCMPGE/FCMPLE together, but overlap is trickier.
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regs_.Map(inst);
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src2));
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FixupBranch unordered = B(CC_VS);
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switch (inst.op) {
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case IROp::FMin:
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fp_.FMIN(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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case IROp::FMax:
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fp_.FMAX(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2));
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break;
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default:
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INVALIDOP;
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break;
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}
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FixupBranch orderedDone = B();
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// Not sure if this path is fast, trying to optimize it to be small but correct.
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// Probably an uncommon path.
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SetJumpTarget(unordered);
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fp_.AND(EncodeRegToDouble(SCRATCHF1), regs_.FD(inst.src1), regs_.FD(inst.src2));
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// SCRATCHF1 = 0xFFFFFFFF if sign bit set on both, 0x00000000 otherwise.
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fp_.CMLT(32, EncodeRegToDouble(SCRATCHF1), EncodeRegToDouble(SCRATCHF1));
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switch (inst.op) {
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case IROp::FMin:
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fp_.SMAX(32, EncodeRegToDouble(SCRATCHF2), regs_.FD(inst.src1), regs_.FD(inst.src2));
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fp_.SMIN(32, regs_.FD(inst.dest), regs_.FD(inst.src1), regs_.FD(inst.src2));
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break;
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case IROp::FMax:
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fp_.SMIN(32, EncodeRegToDouble(SCRATCHF2), regs_.FD(inst.src1), regs_.FD(inst.src2));
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fp_.SMAX(32, regs_.FD(inst.dest), regs_.FD(inst.src1), regs_.FD(inst.src2));
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break;
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default:
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INVALIDOP;
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break;
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}
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// Replace dest with SCRATCHF2 if both were less than zero.
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fp_.BIT(regs_.FD(inst.dest), EncodeRegToDouble(SCRATCHF2), EncodeRegToDouble(SCRATCHF1));
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SetJumpTarget(orderedDone);
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}
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void Arm64JitBackend::CompIR_FCvt(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::FCvtWS:
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CompIR_Generic(inst);
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break;
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case IROp::FCvtSW:
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regs_.Map(inst);
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fp_.SCVTF(regs_.F(inst.dest), regs_.F(inst.src1));
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break;
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case IROp::FCvtScaledWS:
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case IROp::FCvtScaledSW:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FRound(IRInst inst) {
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CONDITIONAL_DISABLE;
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regs_.Map(inst);
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// Invert 0x80000000 -> 0x7FFFFFFF for the NAN result.
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fp_.MVNI(32, EncodeRegToDouble(SCRATCHF1), 0x80, 24);
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fp_.FCMP(regs_.F(inst.src1), regs_.F(inst.src1));
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// Luckily, these already saturate.
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switch (inst.op) {
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case IROp::FRound:
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fp_.FCVTS(regs_.F(inst.dest), regs_.F(inst.src1), ROUND_N);
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break;
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case IROp::FTrunc:
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fp_.FCVTS(regs_.F(inst.dest), regs_.F(inst.src1), ROUND_Z);
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break;
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case IROp::FCeil:
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fp_.FCVTS(regs_.F(inst.dest), regs_.F(inst.src1), ROUND_P);
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break;
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case IROp::FFloor:
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fp_.FCVTS(regs_.F(inst.dest), regs_.F(inst.src1), ROUND_M);
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break;
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default:
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INVALIDOP;
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break;
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}
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// Switch to INT_MAX if it was NAN.
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fp_.FCSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF1, CC_VC);
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}
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void Arm64JitBackend::CompIR_FSat(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::FSat0_1:
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case IROp::FSatMinus1_1:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_FSpecial(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::FSin:
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case IROp::FCos:
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case IROp::FRSqrt:
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case IROp::FRecip:
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case IROp::FAsin:
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CompIR_Generic(inst);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void Arm64JitBackend::CompIR_RoundingMode(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::RestoreRoundingMode:
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RestoreRoundingMode();
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break;
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case IROp::ApplyRoundingMode:
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ApplyRoundingMode();
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break;
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case IROp::UpdateRoundingMode:
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UpdateRoundingMode();
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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