Henrik RydgårdandGitHub 46b25d20a4 Merge pull request #18637 from unknownbrackets/riscv-more ...

Add some more RISC-V extensions to emitter

2023-12-29 19:03:49 +01:00

..

RiscVAsm.cpp

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVCompALU.cpp

riscv: Use a single reg for LO/HI.

2023-08-20 14:49:09 -07:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVCompVec.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVJit.cpp

Back out clearly inconsequential/useless .reserve() calls

2023-12-29 08:27:56 +01:00

RiscVJit.h

IR: Add mini native jit MIPS block profiler.

2023-09-24 23:04:29 -07:00

RiscVRegCache.cpp

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00