mirror of
https://github.com/hrydgard/ppsspp.git
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Henrik RydgårdandClaude Opus 5.5
6207ef9ec7
The operands go in xmm0 and xmm1 and the result comes back in edi. The routine saves nothing: the call site flushes whatever guest state is in the registers it clobbers, the xmms allocated last and rax, rcx, rdx, rsi and rdi, the last two never allocated outside Windows. 32-bit x86 keeps going through the IR interpreter. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
432 lines
13 KiB
C++
432 lines
13 KiB
C++
// Copyright (c) 2023- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include <algorithm>
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#include "Common/CPUDetect.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/x86/X64IRJit.h"
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#include "Core/MIPS/x86/X64IRRegCache.h"
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// This file contains compilation for vector instructions.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace Gen;
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using namespace X64IRJitConstants;
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static bool Overlap(IRReg r1, int l1, IRReg r2, int l2) {
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return r1 < r2 + l2 && r1 + l1 > r2;
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}
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void X64JitBackend::EmitVecConstants() {
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static const float vec4InitData[8][4] = {
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{ 0.0f, 0.0f, 0.0f, 0.0f },
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{ 1.0f, 1.0f, 1.0f, 1.0f },
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{ -1.0f, -1.0f, -1.0f, -1.0f },
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{ 1.0f, 0.0f, 0.0f, 0.0f },
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{ 0.0f, 1.0f, 0.0f, 0.0f },
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{ 0.0f, 0.0f, 1.0f, 0.0f },
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{ 0.0f, 0.0f, 0.0f, 1.0f },
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};
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constants.vec4InitValues = (const Float4Constant *)GetCodePointer();
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for (size_t type = 0; type < ARRAY_SIZE(vec4InitData); ++type) {
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for (int i = 0; i < 4; ++i) {
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uint32_t val;
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memcpy(&val, &vec4InitData[type][i], sizeof(val));
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Write32(val);
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}
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}
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}
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void X64JitBackend::CompIR_VecArith(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Add:
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regs_.Map(inst);
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if (inst.dest == inst.src1) {
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ADDPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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ADDPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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} else if (cpu_info.bAVX) {
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VADDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else {
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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ADDPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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break;
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case IROp::Vec4Sub:
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if (inst.dest == inst.src1) {
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regs_.Map(inst);
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SUBPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (cpu_info.bAVX) {
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regs_.Map(inst);
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VSUBPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVAPS(tempReg, regs_.F(inst.src2));
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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SUBPS(regs_.FX(inst.dest), R(tempReg));
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} else {
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regs_.Map(inst);
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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SUBPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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break;
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case IROp::Vec4Mul:
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regs_.Map(inst);
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if (inst.dest == inst.src1) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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} else if (cpu_info.bAVX) {
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VMULPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else {
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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break;
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case IROp::Vec4Div:
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if (inst.dest == inst.src1) {
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regs_.Map(inst);
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DIVPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (cpu_info.bAVX) {
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regs_.Map(inst);
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VDIVPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVAPS(tempReg, regs_.F(inst.src2));
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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DIVPS(regs_.FX(inst.dest), R(tempReg));
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} else {
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regs_.Map(inst);
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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DIVPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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break;
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case IROp::Vec4Scale:
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// TODO: Handle "aliasing" of sizes.
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if (Overlap(inst.dest, 4, inst.src2, 1) || Overlap(inst.src1, 4, inst.src2, 1))
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DISABLE;
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regs_.Map(inst);
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SHUFPS(regs_.FX(inst.src2), regs_.F(inst.src2), 0);
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if (inst.dest == inst.src1) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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} else if (cpu_info.bAVX) {
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VMULPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else {
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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break;
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case IROp::Vec4Neg:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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VXORPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.signBitAll)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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XORPS(regs_.FX(inst.dest), M(constants.signBitAll)); // rip accessible
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}
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break;
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case IROp::Vec4Abs:
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regs_.Map(inst);
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if (cpu_info.bAVX) {
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VANDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), M(constants.noSignMask)); // rip accessible
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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ANDPS(regs_.FX(inst.dest), M(constants.noSignMask)); // rip accessible
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecAssign(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Init:
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regs_.Map(inst);
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if (inst.src1 == (int)Vec4Init::AllZERO) {
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XORPS(regs_.FX(inst.dest), regs_.F(inst.dest));
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} else {
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MOVAPS(regs_.FX(inst.dest), M(&constants.vec4InitValues[inst.src1])); // rip accessible
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}
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break;
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case IROp::Vec4Shuffle:
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if (regs_.GetFPRLaneCount(inst.src1) == 1 && (inst.src1 & 3) == 0 && inst.src2 == 0) {
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// This is a broadcast. If dest == src1, this won't clear it.
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regs_.SpillLockFPR(inst.src1);
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regs_.MapVec4(inst.dest, MIPSMap::NOINIT);
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} else {
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regs_.Map(inst);
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}
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if (cpu_info.bAVX) {
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VPERMILPS(128, regs_.FX(inst.dest), regs_.F(inst.src1), inst.src2);
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} else {
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if (inst.dest != inst.src1)
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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SHUFPS(regs_.FX(inst.dest), regs_.F(inst.dest), inst.src2);
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}
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break;
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case IROp::Vec4Blend:
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if (cpu_info.bAVX) {
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regs_.Map(inst);
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VBLENDPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2), (uint8_t)inst.constant);
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} else if (cpu_info.bSSE4_1) {
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regs_.Map(inst);
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if (inst.dest == inst.src1) {
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BLENDPS(regs_.FX(inst.dest), regs_.F(inst.src2), (uint8_t)inst.constant);
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} else if (inst.dest == inst.src2) {
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BLENDPS(regs_.FX(inst.dest), regs_.F(inst.src1), (uint8_t)~inst.constant);
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} else {
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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BLENDPS(regs_.FX(inst.dest), regs_.F(inst.src2), (uint8_t)inst.constant);
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}
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} else {
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// Could use some shuffles...
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DISABLE;
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}
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break;
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case IROp::Vec4Mov:
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regs_.Map(inst);
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecHoriz(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Vec4Dot:
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{
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// TODO: Handle "aliasing" of sizes. In theory it should be fine if not dirty...
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if (Overlap(inst.dest, 1, inst.src1, 4) || Overlap(inst.dest, 1, inst.src2, 4))
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DISABLE;
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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if (inst.dest == inst.src1) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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} else if (inst.dest == inst.src2) {
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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} else if (cpu_info.bAVX) {
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VMULPS(128, regs_.FX(inst.dest), regs_.FX(inst.src1), regs_.F(inst.src2));
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} else if (cpu_info.bSSE4_1) {
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MOVAPS(regs_.FX(inst.dest), regs_.F(inst.src1));
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MULPS(regs_.FX(inst.dest), regs_.F(inst.src2));
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}
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// This shuffle can be done in one op for SSE3/AVX, but it's not always faster.
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MOVAPS(tempReg, regs_.F(inst.dest));
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SHUFPS(tempReg, regs_.F(inst.dest), VFPU_SWIZZLE(1, 0, 3, 2));
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ADDPS(regs_.FX(inst.dest), R(tempReg));
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MOVHLPS(tempReg, regs_.FX(inst.dest));
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ADDSS(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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case IROp::Vec4VfpuDot:
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{
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#if PPSSPP_ARCH(AMD64)
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if (!vfpuDot_ || Overlap(inst.dest, 1, inst.src1, 4) || Overlap(inst.dest, 1, inst.src2, 4)) {
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CompIR_Generic(inst);
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break;
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}
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// The operands go to the shared routine in xmm0 and xmm1, and the result comes back in edi.
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// Whatever guest state is in the registers it clobbers gets flushed first: these come last in
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// the allocation order, so usually that's nothing. Then again after the operands are moved,
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// in case they were mapped into one of them.
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auto flushClobbered = [&]() {
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regs_.FlushHostRegs({ RCX, RDX, RSI, RDI }, { XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM14, XMM15 });
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};
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flushClobbered();
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regs_.SpillLockFPR(inst.src1, inst.src2);
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const X64Reg x = regs_.MapVec4(inst.src1);
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const X64Reg y = regs_.MapVec4(inst.src2);
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if (x == XMM1 && y == XMM0) {
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MOVAPS(XMM2, R(XMM0));
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MOVAPS(XMM0, R(XMM1));
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MOVAPS(XMM1, R(XMM2));
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} else if (y == XMM0) {
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MOVAPS(XMM1, R(y));
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MOVAPS(XMM0, R(x));
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} else {
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if (x != XMM0)
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MOVAPS(XMM0, R(x));
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if (y != XMM1)
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MOVAPS(XMM1, R(y));
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}
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regs_.ReleaseSpillLockFPR(inst.src1, inst.src2);
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flushClobbered();
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CALL(vfpuDot_);
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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MOVD_xmm(regs_.FX(inst.dest), R(EDI));
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#else
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// 32-bit x86 has too few registers for the shared routine.
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CompIR_Generic(inst);
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#endif
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break;
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}
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default:
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INVALIDOP;
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break;
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}
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}
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void X64JitBackend::CompIR_VecPack(IRInst inst) {
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CONDITIONAL_DISABLE;
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// Only SSE2 here. A destination overlapping the source goes the slow way, it's rare.
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switch (inst.op) {
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case IROp::Vec4Pack32To8:
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case IROp::Vec4Pack31To8:
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{
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if (Overlap(inst.dest, 1, inst.src1, 4)) {
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DISABLE;
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}
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// The top byte of each lane, packed into one lane. For 31, the byte below the sign, with
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// negative lanes clamped to zero: the arithmetic shift makes them negative, and PACKUSWB
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// saturates them to 0.
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVDQA(tempReg, regs_.F(inst.src1));
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if (inst.op == IROp::Vec4Pack31To8)
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PSRAD(tempReg, 23);
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else
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PSRLD(tempReg, 24);
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PACKSSDW(tempReg, R(tempReg));
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PACKUSWB(tempReg, R(tempReg));
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MOVDQA(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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case IROp::Vec2Pack32To16:
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case IROp::Vec2Pack31To16:
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{
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if (Overlap(inst.dest, 1, inst.src1, 2)) {
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DISABLE;
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}
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// The top 16 bits of each lane (for 31, the 16 below the sign, with negative lanes clamped
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// to zero), packed into one lane. The arithmetic shift keeps them in PACKSSDW's range, so
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// the bits come through unchanged.
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVDQA(tempReg, regs_.F(inst.src1));
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if (inst.op == IROp::Vec2Pack31To16) {
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PSRAD(tempReg, 31);
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PANDN(tempReg, regs_.F(inst.src1));
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PSLLD(tempReg, 1);
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}
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PSRAD(tempReg, 16);
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PACKSSDW(tempReg, R(tempReg));
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MOVDQA(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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case IROp::Vec4Unpack8To32:
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{
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if (Overlap(inst.dest, 4, inst.src1, 1)) {
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DISABLE;
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}
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// Each byte into the top of a lane: duplicate bytes, then words, then shift the rest out.
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVDQA(tempReg, regs_.F(inst.src1));
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PUNPCKLBW(tempReg, R(tempReg));
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PUNPCKLWD(tempReg, R(tempReg));
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PSLLD(tempReg, 24);
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MOVDQA(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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case IROp::Vec2Unpack16To32:
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case IROp::Vec2Unpack16To31:
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{
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if (Overlap(inst.dest, 2, inst.src1, 1)) {
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DISABLE;
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}
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// Each half into the top of a lane, shifted down one more for 31.
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVDQA(tempReg, regs_.F(inst.src1));
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PUNPCKLWD(tempReg, R(tempReg));
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PSLLD(tempReg, 16);
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if (inst.op == IROp::Vec2Unpack16To31)
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PSRLD(tempReg, 1);
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MOVDQA(regs_.FX(inst.dest), R(tempReg));
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break;
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}
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case IROp::Vec4DuplicateUpperBitsAndShift1:
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{
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if (inst.dest != inst.src1 && Overlap(inst.dest, 4, inst.src1, 4)) {
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DISABLE;
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}
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// v |= v >> 8; v |= v >> 16; v >>= 1, which turns 0xFF000000 into 0x7FFFFFFF.
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X64Reg tempReg = regs_.MapWithFPRTemp(inst);
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MOVDQA(tempReg, regs_.F(inst.src1));
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PSRLD(tempReg, 8);
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POR(tempReg, regs_.F(inst.src1));
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MOVDQA(regs_.FX(inst.dest), R(tempReg));
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PSRLD(tempReg, 16);
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POR(regs_.FX(inst.dest), R(tempReg));
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PSRLD(regs_.FX(inst.dest), 1);
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break;
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}
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default:
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INVALIDOP;
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break;
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}
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}
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} // namespace MIPSComp
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#endif
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