Henrik RydgårdandClaude Fable 5.1 b16cd9a734 VFPU: vsgn of a denormal is zero ...

In the interpreter, the IR interpreter, every backend's FSign and the x86
JIT's own vsgn. Recorded in cpu/vfpu/specials.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

2026-09-22 14:10:22 -06:00

..

RiscVAsm.cpp

Merge pull request #22336 from hrydgard/misc-work

2026-09-22 13:15:12 -06:00

RiscVCompALU.cpp

MIPS: INT_MIN / -1 leaves HI at zero, like the hardware

2026-09-22 11:02:20 -06:00

RiscVCompBranch.cpp

x86jit: Stub out op categories to files.

2023-08-20 22:28:54 -07:00

RiscVCompFPU.cpp

VFPU: vsgn of a denormal is zero

2026-09-22 14:10:22 -06:00

RiscVCompLoadStore.cpp

irjit: Fix safety of kernel bit memory addresses.

2023-09-24 10:18:55 -07:00

RiscVCompSystem.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVCompVec.cpp

riscv: Implement Zfa encoding.

2023-12-29 09:42:23 -08:00

RiscVJit.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVJit.h

JIT/IRJit: Delete an old "function preloading" experiment

2025-06-11 15:45:18 +02:00

RiscVRegCache.cpp

RISC-V, LoongArch64: fix caller-saved FPRs, div by zero, and more

2026-09-22 08:39:25 -06:00

RiscVRegCache.h

irjit: Add facility for native reg transfer.

2023-09-24 16:28:29 -07:00